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Institution Date Title Author
南台科技大學 1994-06 Efficient diagnostic fault simulation for sequential circuits Jer Min Jou; Shung-Chih Chen; 孫建明;陳順智
南台科技大學 1994-05 A Super Fast and Memory Efficient Diagnostic Simulation Algorithm for Combinational Circuits Jer Min Jou; Shung-Chih Chen; Ren-Der Chen; 陳順智
南台科技大學 1994-04 A Fast and Memory-Efficient Diagnostic Fault Simulation for Sequential Circuits Jer Min Jou; Shung-Chih Chen; 孫建明;陳順智
南台科技大學 1993-05 PARCRIPT: a very fast combinational fault simulator Jer Min Jou; Shung-Chih Chen; 孫建明;陳順智
南台科技大學 1992-03 An Efficient VHDL Simulator with Two-Simulation-Run Ability Jer Min Jou; Shung-Chih Chen
南台科技大學 1992-01 MASS: An Integrated Approach to High Level Synthesis Jer Min Jou; S. R. Kuang; Shung-Chih Chen
南台科技大學 1991-12 An Efficient Mixed-level VHDL Simulator with Robust Debugging Capability Jer Min Jou; Shung-Chih Chen

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