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Institution Date Title Author
中原大學 2009-11 Design a Fully MIPS32 ISA Processor with Corresponding Verification Environment Slo-Li Chu; Chih-Nan Hsu; Geng-Siao Li
中原大學 2009-05 MediaMem: An ESL Implementation of a Memory Subsystem for High-Bandwidth Required Multimedia SoC Systems Slo-Li Chu; Min-Jen Lo; Yen-Hsiang Huang
中原大學 2009 Design a Hardware Mechanism to Utilize Multiprocessors on a Uni-processor Operating System Slo-Li Chu; Chih-Chieh Hsiao; Pin-Hua Chiu
中原大學 2004-04 Improving Workload Balance and Code Optimization on Processor-in-Memory Systems Slo-Li Chu;Tsung-Chuan Huang;Lan-Chi Lee
中原大學 2004-03 SBATCH: An Integrated Statement-Based Parallelizing Compiler for Tightly-Coupled Heterogeneous Environments Slo-Li Chu
國立中山大學 2004-03 A new code scheduling mechanism for a processor-in-memory architecture Slo-Li Chu;Tsung-Chuan Huang
中原大學 2004-01 SAGE: An Automatic Analyzing System for a New High-Performance SoC Architecture––Processor-in-Memory Slo-Li Chu;Tsung-Chuan Huang
國立中山大學 2004 Improving workload balance and code optimization on processor-in-memory systems Slo-Li Chu; Tsung-Chuan Huang; Lan-Chi Lee
國立中山大學 2004 SAGE: An automatic Analyzing system for a new high-performance SoC architecture-Processor-in-Memory Slo-Li Chu; Tsung-Chuan Huang
國立中山大學 2003-06 A list-based low power scheduling technique for intelligent memory system Tsung-Chuan Huang;Slo-Li Chu;Yu-Wen Shu

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