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教育部委托研究计画 计画执行:国立台湾大学图书馆
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"su chauchin"的相关文件
显示项目 16-25 / 42 (共5页)
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| 國立交通大學 |
2014-12-08T15:32:53Z |
A Near-Threshold 480 MHz 78 mu W All-Digital PLL With a Bootstrapped DCO
|
Ho, Yingchieh; Yang, Yu-Sheng; Chang, ChiaChi; Su, Chauchin |
| 國立交通大學 |
2014-12-08T15:29:01Z |
A 0.09 mu W Low Power Front-End Biopotential Amplifier for Biosignal Recording
|
Tseng, Yuhwai; Ho, Yingchieh; Kao, Shuoting; Su, Chauchin |
| 國立交通大學 |
2014-12-08T15:28:35Z |
Cumulative Differential Non linearity Testing of ADCs
|
Chen, Hungkai; Ho, Yingchieh; Su, Chauchin |
| 國立交通大學 |
2014-12-08T15:25:28Z |
Oscillation ring based interconnect test scheme for SOC
|
Li, Katherine Shu-Min; Lee, Chung Len; Su, Chauchin; Chen, Jwu E. |
| 國立交通大學 |
2014-12-08T15:24:42Z |
A digital BIST methodology for spread spectrum clock generators
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Chou, Maohsuan; Hsu, Jenchien; Su, Chauchin |
| 國立交通大學 |
2014-12-08T15:22:37Z |
A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters
|
Ho, Yingchieh; Su, Chauchin |
| 國立交通大學 |
2014-12-08T15:22:23Z |
Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique
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Ho, Yingchieh; Chang, Chiachi; Su, Chauchin |
| 國立交通大學 |
2014-12-08T15:20:50Z |
A 1.5V 7.5uW Programmable Gain Amplifier for Multiple Biomedical Signal Acquisition
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Kao, Shuo-Ting; Lu, Hungwen; Su, ChauChin |
| 國立交通大學 |
2014-12-08T15:15:32Z |
Passive reduced-order macro-modeling for linear time-delay interconnect systems
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Tseng, Wenliang; Liu, Chien-Nan Jimmy; Su, Chauchin |
| 國立交通大學 |
2014-12-08T15:15:31Z |
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
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Li, Katherine Shu-Min; Su, Chauchin; Chang, Yao-Wen; Lee, Chung-Len; Chen, Jwu E. |
显示项目 16-25 / 42 (共5页)
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