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"su jun ren"
Showing items 1-8 of 8 (1 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:48:20Z |
Delay-Line Based Fast-Locking All-Digital Pulsewidth-Control Circuit with Programmable Duty Cycle
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Su, Jun-Ren; Liao, Te-Wen; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-12T02:38:11Z |
全數位快速鎖定且具可程式工作週期之脈寬調變電路
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蘇俊仁; Su, Jun-Ren; 洪崇智; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-08T15:35:46Z |
Sub-Sampling Charge Pump and Random Pulsewidth Matching Technique for Frequency Synthesizer
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Liao, Te-Wen; Su, Jun-Ren; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-08T15:35:45Z |
Ring-VCO Based Low Noise and Low Spur Frequency Synthesizer
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Liao, Te-Wen; Su, Jun-Ren; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-08T15:31:30Z |
All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle
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Su, Jun-Ren; Liao, Te-Wen; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-08T15:29:24Z |
Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
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Liao, Te-Wen; Su, Jun-Ren; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-08T15:28:41Z |
Low-Spur Technique For Integer-N Phase-Locked Loop
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Liao, Te-Wen; Su, Jun-Ren; Hung, Chung-Chih |
| 國立交通大學 |
2014-12-08T15:28:28Z |
Random Pulsewidth Matching Frequency Synthesizer With Sub-Sampling Charge Pump
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Liao, Te-Wen; Chen, Chia-Min; Su, Jun-Ren; Hung, Chung-Chih |
Showing items 1-8 of 8 (1 Page(s) Totally)
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