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"su k w"的相關文件
顯示項目 111-130 / 130 (共3頁)
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| 國立臺灣科技大學 |
2013 |
Design and implementation of a fixed-mobile convergent music search engine (FMC-MUSE)
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Leu, J.-S.;Changfan, C.;Su, K.-W.;Chen, C.-F. |
| 國立臺灣科技大學 |
2012 |
Design and implementation of a mobile ambient intelligence based Mesoscale Weather Forecasting System
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Chen, C.-T.;Leu, J.-S.;Su, K.-W.;Zhu, Z.-Y.;Chiang, T.-H. |
| 國立交通大學 |
2007-04-01 |
Statistical properties of experimental coherent waves in microcavity lasers: Analogous study of quantum billiard wave functions
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Chen, C. C.; Liu, C. C.; Su, K. W.; Lu, T. H.; Chen, Y. F.; Huang, K. F. |
| 國立臺灣大學 |
2006-04 |
Generation of hydrocarbon gases and CO2 from a humic coal: Experimental study on the effect of water, minerals and transition-metals
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Su, K.W.; Shen, J.C.; Chang, Y.J.; Huang*, W.L. |
| 國立臺灣大學 |
2006-02 |
Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1 nm) gate oxide
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Lin, C.H.; Kuo, J.B.; Su, K.W.; Liu, S. |
| 國立臺灣大學 |
1997-10 |
Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects
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Kuo, J.B.; Su, K.W. |
| 臺大學術典藏 |
1997-10 |
Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects
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Kuo, J.B.; Su, K.W.; Kuo, J.B.; Su, K.W.; KuoJB |
| 國立臺灣大學 |
1996-09 |
Analytical current conduction model for accumulation-mode SOI PMOS devices
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Su, K.W.; Kuo, J.B. |
| 國立臺灣大學 |
1995-10 |
An analytical delayed-turn-off model for 6H-SiC buried-channel NMOS devices considering incomplete ionization
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Su, K.W.; Kuo, J.B. |
| 國立臺灣大學 |
1995-10 |
Accumulation-type vs. inversion-type: narrow channel effect in VLSI mesa-isolated fully-depleted ultra-thin SOI PMOS devices
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Su, K.W.; Kuo, J.B. |
| 國立臺灣大學 |
1995-09 |
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems
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Kuo, J.B.; Lou, J.H.; Su, K.W. |
| 臺大學術典藏 |
1995-09 |
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems
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Kuo, J.B.; Lou, J.H.; Su, K.W.; Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB |
| 國立臺灣大學 |
1994-12 |
A 1.5 V 10 MHz BiCMOS quasi-digital vector modulator for wireless communication IC
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Su, K.W.; Chen, Y.G.; Lai, C.S.; Kuo, J.B.; Wu, J.S.; Tso, H.W. |
| 國立臺灣大學 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
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Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB |
| 國立臺灣大學 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S. |
| 臺大學術典藏 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB |
| 國立臺灣大學 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
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Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
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KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 國立臺灣大學 |
1993-03 |
BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
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Chen, S.S.; Chiang, C.S.; Su, K.W.; Kuo, J.B. |
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