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Showing items 1-5 of 5 (1 Page(s) Totally)
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| 國立交通大學 |
2018-08-21T05:57:09Z |
Low-Trigger ESD Protection Design with Latch-Up Immunity for 5-V CMOS Application by Drain Engineering
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Chiang, Chun; Chang, Ping-Chen; Chao, Mei-Ling; Tang, Tien-Hao; Su, Kuan-Cheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:18Z |
Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology
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Wang, Chang-Tzu; Ker, Ming-Dou; Tang, Tien-Hao; Su, Kuan-Cheng |
| 國立交通大學 |
2014-12-08T15:25:06Z |
ESC robustness of 40-V CMOS devices with/without drift implant
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Chang, Wei-Jen; Ker, Ming-Dou; Lai, Tai-Hsiang; Tang, Tien-Hao; Su, Kuan-Cheng |
| 國立交通大學 |
2014-12-08T15:12:36Z |
The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process
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Chang, Wei-Jen; Ker, Ming-Dou; Lai, Tai-Xiang; Tang, Tien-Hao; Su, Kuan-Cheng |
| 義守大學 |
2009 |
Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology
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Wang, Chang-Tzu ; Ker, Ming-Dou ; Tang, Tien-Hao ; Su, Kuan-Cheng |
Showing items 1-5 of 5 (1 Page(s) Totally)
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