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"su ming chiuan"
Showing items 1-6 of 6 (1 Page(s) Totally)
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| 國立交通大學 |
2019-04-03T06:40:10Z |
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques
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Chang, Chia-Wen; Lo, Kai-Yu; Ibrahim, Hossameldin A.; Su, Ming-Chiuan; Chu, Yuan-Hua; Jou, Shyh-Jye |
| 國立交通大學 |
2015-11-26T00:55:33Z |
應用於序列傳輸系統之突發式時脈資料回復電路與全數位式展頻時脈產生器
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蘇明銓; Su, Ming-Chiuan; 周世傑; 陳巍仁; Jou, Shyh-Jye; Chen, Wei-Zen |
| 國立交通大學 |
2015-07-21T08:31:06Z |
A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter Suppression
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Su, Ming-Chiuan; Chen, Wei-Zen; Wu, Pei-Si; Chen, Yu-Hsian; Lee, Chao-Cheng; Jou, Shyh-Jye |
| 國立交通大學 |
2015-07-21T08:29:26Z |
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs
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Su, Ming-Chiuan; Jou, Shyh-Jye; Chen, Wei-Zen |
| 國立交通大學 |
2015-07-21T08:28:41Z |
A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression
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Su, Ming-Chiuan; Chen, Wei-Zen; Wu, Pei-Si; Chen, Yu-Hsiang; Lee, Chao-Cheng; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-12T01:27:13Z |
適用於展頻時脈產生器之全數位鎖相迴路
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蘇明銓; Su, Ming-Chiuan; 周世傑; Jou, Shyh-Jye |
Showing items 1-6 of 6 (1 Page(s) Totally)
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