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Showing items 21-30 of 199  (20 Page(s) Totally)
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Institution Date Title Author
國立交通大學 2019-04-03T06:44:23Z New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs Wu, Shu-Hua; Yu, Chang-Hung; Su, Pin
國立交通大學 2019-04-03T06:42:08Z Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs Yu, Kuan-Chin; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2019-04-03T06:35:52Z Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process Variations Wu, Shu-Hua; Yu, Chien-Lin; Yu, Chang-Hung; Su, Pin
國立交通大學 2019-04-02T06:04:45Z Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations. Chang, Chia-Ning; Chen, Yin-Nien; Huang, Po-Tsang; Su, Pin; Chuang, Ching-Te
國立交通大學 2019-04-02T06:04:21Z A New and Simple DC Method for Thermal-Resistance Extraction of Scaled FinFET Devices Huang, Wei-Cheng; Su, Pin
國立交通大學 2019-04-02T06:04:21Z Interface Discrete Trap Induced Variability for Negative Capacitance FinFETs Lee, Ho-Pei; Tseng, Kuei-Yang; Su, Pin
國立交通大學 2019-04-02T06:00:45Z Intrinsic Difference Between 2-D Negative-Capacitance FETs With Semiconductor-on-Insulator and Double-Gate Structures You, Wei-Xiang; Su, Pin
國立交通大學 2019-04-02T05:59:08Z Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2019-04-02T05:58:35Z Experimental Analysis of Quasi-Ballistic Transport in Advanced Si nFinFETs Using New Extraction Method Lin, Ming-Huei; Su, Pin; Chen, Hou-Yu; Lu, Jen-Hsiang; Chang, Vincent S.; Yang, Shyh-Horng
國立交通大學 2019-04-02T05:58:12Z Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te

Showing items 21-30 of 199  (20 Page(s) Totally)
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