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Showing items 26-35 of 199  (20 Page(s) Totally)
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Institution Date Title Author
國立交通大學 2019-04-02T06:04:21Z Interface Discrete Trap Induced Variability for Negative Capacitance FinFETs Lee, Ho-Pei; Tseng, Kuei-Yang; Su, Pin
國立交通大學 2019-04-02T06:00:45Z Intrinsic Difference Between 2-D Negative-Capacitance FETs With Semiconductor-on-Insulator and Double-Gate Structures You, Wei-Xiang; Su, Pin
國立交通大學 2019-04-02T05:59:08Z Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2019-04-02T05:58:35Z Experimental Analysis of Quasi-Ballistic Transport in Advanced Si nFinFETs Using New Extraction Method Lin, Ming-Huei; Su, Pin; Chen, Hou-Yu; Lu, Jen-Hsiang; Chang, Vincent S.; Yang, Shyh-Horng
國立交通大學 2019-04-02T05:58:12Z Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2019-04-02T05:58:09Z Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2018-08-21T05:56:55Z Ultra-Low Voltage Mixed TFET-MOSFET 8T SRAM Cell Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2018-08-21T05:56:52Z Impacts of Work Function Variation and Line Edge Roughness on Hybrid TFET-MOSFET Monolithic 3D SRAMs Wang, Jian-Hao; Su, Pin; Chuang, Ching-Te
國立交通大學 2018-08-21T05:56:52Z Evaluation of Analog Performance of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) MOSFETs Lee, Hung-Yi; Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te
國立交通大學 2018-08-21T05:56:52Z Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm Node Yu, Chang-Hung; Zheng, Jun-Teng; Su, Pin; Chuang, Ching-Te

Showing items 26-35 of 199  (20 Page(s) Totally)
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