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"su pin"
Showing items 36-45 of 199 (20 Page(s) Totally)
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| 國立交通大學 |
2018-08-21T05:56:52Z |
Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs
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Lee, Ho-Pei; Yu, Chien-Lin; You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Exploration and Evaluation of TCAM with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
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Tu, Meng-Hsuan; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Design Space Exploration Considering Back-Gate Biasing Effects for Negative-Capacitance Transition-Metal-Dichalcogenide (TMD) Field-Effect Transistors
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You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2018-08-21T05:54:20Z |
Design Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect Transistors
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You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2018-08-21T05:53:58Z |
Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:53:27Z |
Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors
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You, Wei-Xiang; Tsai, Chih-Peng; Su, Pin |
| 國立交通大學 |
2018-08-21T05:52:50Z |
Suppressed Fin-LER Induced Variability in Negative Capacitance FinFETs
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Lee, Ho-Pei; Su, Pin |
| 國立成功大學 |
2018-03 |
Validating the creative self-efficacy student scale with a Taiwanese sample: An item response theory-based investigation
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Hung;Su-Pin |
| 國立交通大學 |
2018-01-24T07:42:42Z |
鰭狀式場效電晶體之特性分析及堆疊式環狀閘極場效電晶體於邏輯電路應用中最佳堆疊層數之探討
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黃威程; 蘇彬; Huang, Wei-Cheng; Su, pin |
| 國立交通大學 |
2018-01-24T07:42:15Z |
二維過渡金屬硫屬化合物及堆疊式奈米線元件之靜態隨機存取記憶體分析與研究
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鄭峻騰; 蘇彬; Zheng, Chun-Teng; Su Pin |
Showing items 36-45 of 199 (20 Page(s) Totally)
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