| 國立交通大學 |
2018-01-24T07:40:33Z |
鍺通道超薄絕緣層負電容金氧半場效電晶體之設計空間及負電容鰭狀電晶體之鰭邊緣粗糙引發之變異度分析
|
李禾培; 蘇彬; Lee, Ho-Pei; Su, Pin |
| 國立交通大學 |
2018-01-24T07:38:55Z |
混合穿隧式場效電晶體與鰭式場效電晶體的三態內容可定址記憶體電路超低壓應用之研究與分析
|
杜孟軒; 莊景德; 蘇彬; Tu, Meng-Hsuan; Chuang,Ching-Te; Su,Pin |
| 國立交通大學 |
2018-01-24T07:38:53Z |
量子電容效應於超薄單閘極與雙閘極及閘極全包覆式三五族金氧半場效電晶體 閘極反轉層電容値之比較與模型建立
|
沈仕倫; 蘇彬; Shen, Shih-Lun; Su, Pin |
| 國立交通大學 |
2018-01-24T07:38:53Z |
超薄絕緣三五族金氧半場效電晶體與負電容場效電晶體之量子次臨界模型建立
|
余建霖; 蘇彬; Yu, Chien-Lin; Su, Pin |
| 國立交通大學 |
2018-01-24T07:38:51Z |
超薄絕緣層異質三五族與鍺通道金氧半場效電晶體及單層與多層二維過渡金屬硫屬化合物之邏輯電路及靜態隨機存取記憶體之研究與分析
|
余昌鴻; 蘇彬; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2018-01-24T07:38:13Z |
全包覆式閘極三五族穿隧式電晶體的直徑最佳化及短通道效應之理論探討
|
王佑瑋; 蘇彬; Wang, Yu-Wei; Su, Pin |
| 國立交通大學 |
2018-01-24T07:36:57Z |
高遷移率通道三閘極電晶體 之靜電完整性的理論研究
|
吳杼樺; 蘇彬; Wu, Shu-Hua; Su, Pin |
| 國立交通大學 |
2017-04-21T06:56:35Z |
A Compact Subthreshold Model for Short-Channel Monolayer Transition Metal Dichalcogenide Field-Effect Transistors
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2017-04-21T06:56:15Z |
Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:55:34Z |
Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET
|
Hsu, Chih-Wei; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin |
| 國立交通大學 |
2017-04-21T06:50:14Z |
Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFET
|
Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:50:10Z |
Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
|
Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:50:05Z |
Investigation of BTI Reliability for Monolithic 3D 6T SRAM with Ultra-thin-body GeOI MOSFETs
|
Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:57Z |
Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and Logic Circuits
|
Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:47Z |
UTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliability
|
Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:44Z |
Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its Suppression
|
Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:49:30Z |
Investigation and Benchmark of Intrinsic Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body III-V-on-Insulator n-MOSFETs
|
Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Stability Optimization of Monolithic 3-D MoS2-n/WSe2-p SRAM Cells for Superthreshold and Near-/Sub-threshold Applications
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:25Z |
Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:09Z |
Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap
|
Hu, Vita Pi-Ho; Lo, Chang-Ting; Sachid, Angada B.; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2017-04-21T06:49:08Z |
Accurate modeling and characterization of mobility in tensile and compressive stress for state-of-the-art manufacturing NMOSFETs
|
Wang, J. -S.; Chen, William P. N.; Shih, C. -H.; Lien, C.; Su, Pin; Sheu, Y. M.; Chao, Donald Y. -S.; Goto, K. |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness
|
Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:02Z |
Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:48:32Z |
Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices
|
Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:48:17Z |
Simulation of Grain-Boundary Induced V-th Variability in Stackable NAND Flash Using a Voronoi Approach
|
Yang, Ching-Wei; Chao, Shao-Heng; Su, Pin |
