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"su pin"
Showing items 6-15 of 199 (20 Page(s) Totally)
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| 國立交通大學 |
2020-10-05T02:01:28Z |
Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach
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Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2020-03-02T03:23:33Z |
Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance
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Huang, Shih-En; Lin, Shih-Han; Su, Pin |
| 國立交通大學 |
2020-03-01 |
Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution
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Liu, You-Sheng; Su, Pin |
| 國立交通大學 |
2020-02-02T23:55:33Z |
Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applications
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Tseng, Kuei-Yang; You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2020-02-02T23:55:33Z |
Impact of Multi-Domain Interaction on ON-State Characteristics of MFIS-Type 2D Negative-Capacitance FETs
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Lu, Po-Sheng; Lin, Chia-Chen; Su, Pin |
| 國立交通大學 |
2020-02-02T23:55:33Z |
Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs
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Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2020-01-02T00:03:29Z |
Investigation of Ferroelectric Granularity for Double-Gate Negative-Capacitance FETs Considering Position and Number Fluctuations
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Fan, Che-Lun; Tseng, Kuei-Yang; Liu, You-Sheng; Su, Pin |
| 國立交通大學 |
2020-01-01 |
A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
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Hu, Chenming; Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2019-12-13T01:12:54Z |
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells
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Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-10-05T00:08:43Z |
Depolarization Field in Ferroelectric Nonvolatile Memory Considering Minor Loop Operation
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You, Wei-Xiang; Su, Pin |
Showing items 6-15 of 199 (20 Page(s) Totally)
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