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"su pin"的相关文件
显示项目 126-135 / 199 (共20页) << < 8 9 10 11 12 13 14 15 16 17 > >> 每页显示[10|25|50]项目
| 國立交通大學 |
2014-12-08T15:36:50Z |
Built-in Effective Body-Bias Effect in Ultra-Thin-Body Hetero-Channel III-V-on-Insulator n-MOSFETs
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Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2014-12-08T15:36:16Z |
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:11Z |
FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientation
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Hu, Vita Pi-Ho; Fan, Ming-Long; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:35:55Z |
Investigation of Backgate-Bias Dependence of Threshold-Voltage Sensitivity to Process and Temperature Variations for Ultra-Thin-Body Hetero-Channel MOSFETs
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Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2014-12-08T15:35:52Z |
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits
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Fan, Ming-Long; Yang, Shao-Yu; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:35:20Z |
Simulation and Investigation of Random Grain-Boundary-Induced Variabilities for Stackable NAND Flash Using 3-D Voronoi Grain Patterns
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Yang, Ching-Wei; Su, Pin |
| 國立交通大學 |
2014-12-08T15:35:18Z |
Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits
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Yang, Shao-Yu; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:43Z |
Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices
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Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:32:43Z |
Source/Drain Series Resistance Induced Feedback Effect on Drain Current Mismatch and Its Implication
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Kuo, Jack J. -Y.; Fan, Ming-Long; Lee, Wei; Su, Pin |
| 國立交通大學 |
2014-12-08T15:32:43Z |
Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs
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Tsai, Ming-Fu; Fan, Ming-Long; Pao, Chia-Hao; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
显示项目 126-135 / 199 (共20页) << < 8 9 10 11 12 13 14 15 16 17 > >> 每页显示[10|25|50]项目
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