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机构 日期 题名 作者
國立交通大學 2014-12-08T15:36:50Z Built-in Effective Body-Bias Effect in Ultra-Thin-Body Hetero-Channel III-V-on-Insulator n-MOSFETs Yu, Chang-Hung; Su, Pin
國立交通大學 2014-12-08T15:36:16Z Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:36:11Z FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientation Hu, Vita Pi-Ho; Fan, Ming-Long; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:35:55Z Investigation of Backgate-Bias Dependence of Threshold-Voltage Sensitivity to Process and Temperature Variations for Ultra-Thin-Body Hetero-Channel MOSFETs Yu, Chang-Hung; Su, Pin
國立交通大學 2014-12-08T15:35:52Z Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits Fan, Ming-Long; Yang, Shao-Yu; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:35:20Z Simulation and Investigation of Random Grain-Boundary-Induced Variabilities for Stackable NAND Flash Using 3-D Voronoi Grain Patterns Yang, Ching-Wei; Su, Pin
國立交通大學 2014-12-08T15:35:18Z Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits Yang, Shao-Yu; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:43Z Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2014-12-08T15:32:43Z Source/Drain Series Resistance Induced Feedback Effect on Drain Current Mismatch and Its Implication Kuo, Jack J. -Y.; Fan, Ming-Long; Lee, Wei; Su, Pin
國立交通大學 2014-12-08T15:32:43Z Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs Tsai, Ming-Fu; Fan, Ming-Long; Pao, Chia-Hao; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te

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