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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"su pin"的相關文件
顯示項目 16-25 / 199 (共20頁)
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| 國立交通大學 |
2019-08-02T02:18:32Z |
Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effect
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Huang, Shih-En; Yu, Chien-Lin; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Investigation of Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors
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You, Wei-Xiang; Tsai, Chih-Peng; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Device Structural Effects on Negative-Capacitance FETs
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2019-05-02T00:25:52Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2019-04-03T06:44:23Z |
New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs
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Wu, Shu-Hua; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2019-04-03T06:42:08Z |
Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs
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Yu, Kuan-Chin; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-03T06:35:52Z |
Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process Variations
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Wu, Shu-Hua; Yu, Chien-Lin; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2019-04-02T06:04:45Z |
Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations.
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Chang, Chia-Ning; Chen, Yin-Nien; Huang, Po-Tsang; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-02T06:04:21Z |
A New and Simple DC Method for Thermal-Resistance Extraction of Scaled FinFET Devices
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Huang, Wei-Cheng; Su, Pin |
顯示項目 16-25 / 199 (共20頁)
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