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"su pin"的相关文件
显示项目 11-20 / 199 (共20页)
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| 國立交通大學 |
2020-02-02T23:55:33Z |
Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2020-01-02T00:03:29Z |
Investigation of Ferroelectric Granularity for Double-Gate Negative-Capacitance FETs Considering Position and Number Fluctuations
|
Fan, Che-Lun; Tseng, Kuei-Yang; Liu, You-Sheng; Su, Pin |
| 國立交通大學 |
2020-01-01 |
A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
|
Hu, Chenming; Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2019-12-13T01:12:54Z |
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-10-05T00:08:43Z |
Depolarization Field in Ferroelectric Nonvolatile Memory Considering Minor Loop Operation
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2019-08-02T02:18:32Z |
Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effect
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Huang, Shih-En; Yu, Chien-Lin; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Investigation of Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors
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You, Wei-Xiang; Tsai, Chih-Peng; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Device Structural Effects on Negative-Capacitance FETs
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2019-05-02T00:25:52Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
显示项目 11-20 / 199 (共20页)
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