| 國立交通大學 |
2019-08-02T02:18:32Z |
Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effect
|
Huang, Shih-En; Yu, Chien-Lin; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Investigation of Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors
|
You, Wei-Xiang; Tsai, Chih-Peng; Su, Pin |
| 國立交通大學 |
2019-05-02T00:26:47Z |
Device Structural Effects on Negative-Capacitance FETs
|
Su, Pin; You, Wei-Xiang |
| 國立交通大學 |
2019-05-02T00:25:52Z |
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
|
You, Wei-Xiang; Su, Pin; Hu, Chenming |
| 國立交通大學 |
2019-04-03T06:44:23Z |
New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs
|
Wu, Shu-Hua; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2019-04-03T06:42:08Z |
Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs
|
Yu, Kuan-Chin; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-03T06:35:52Z |
Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process Variations
|
Wu, Shu-Hua; Yu, Chien-Lin; Yu, Chang-Hung; Su, Pin |
| 國立交通大學 |
2019-04-02T06:04:45Z |
Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations.
|
Chang, Chia-Ning; Chen, Yin-Nien; Huang, Po-Tsang; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-02T06:04:21Z |
A New and Simple DC Method for Thermal-Resistance Extraction of Scaled FinFET Devices
|
Huang, Wei-Cheng; Su, Pin |
| 國立交通大學 |
2019-04-02T06:04:21Z |
Interface Discrete Trap Induced Variability for Negative Capacitance FinFETs
|
Lee, Ho-Pei; Tseng, Kuei-Yang; Su, Pin |
| 國立交通大學 |
2019-04-02T06:00:45Z |
Intrinsic Difference Between 2-D Negative-Capacitance FETs With Semiconductor-on-Insulator and Double-Gate Structures
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2019-04-02T05:59:08Z |
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
|
Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-02T05:58:35Z |
Experimental Analysis of Quasi-Ballistic Transport in Advanced Si nFinFETs Using New Extraction Method
|
Lin, Ming-Huei; Su, Pin; Chen, Hou-Yu; Lu, Jen-Hsiang; Chang, Vincent S.; Yang, Shyh-Horng |
| 國立交通大學 |
2019-04-02T05:58:12Z |
Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2019-04-02T05:58:09Z |
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications
|
Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:55Z |
Ultra-Low Voltage Mixed TFET-MOSFET 8T SRAM Cell
|
Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Impacts of Work Function Variation and Line Edge Roughness on Hybrid TFET-MOSFET Monolithic 3D SRAMs
|
Wang, Jian-Hao; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Evaluation of Analog Performance of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) MOSFETs
|
Lee, Hung-Yi; Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm Node
|
Yu, Chang-Hung; Zheng, Jun-Teng; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs
|
Lee, Ho-Pei; Yu, Chien-Lin; You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Exploration and Evaluation of TCAM with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
|
Tu, Meng-Hsuan; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Design Space Exploration Considering Back-Gate Biasing Effects for Negative-Capacitance Transition-Metal-Dichalcogenide (TMD) Field-Effect Transistors
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2018-08-21T05:54:20Z |
Design Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect Transistors
|
You, Wei-Xiang; Su, Pin |
| 國立交通大學 |
2018-08-21T05:53:58Z |
Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs
|
Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te |
