English  |  正體中文  |  简体中文  |  0  
???header.visitor??? :  51072206    ???header.onlineuser??? :  986
???header.sponsordeclaration???
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
???ui.leftmenu.abouttair???

???ui.leftmenu.bartitle???

???index.news???

???ui.leftmenu.copyrighttitle???

???ui.leftmenu.link???

"su pin"???jsp.browse.items-by-author.description???

???jsp.browse.items-by-author.back???
???jsp.browse.items-by-author.order1??? ???jsp.browse.items-by-author.order2???

Showing items 66-75 of 199  (20 Page(s) Totally)
<< < 2 3 4 5 6 7 8 9 10 11 > >>
View [10|25|50] records per page

Institution Date Title Author
國立交通大學 2017-04-21T06:49:08Z Accurate modeling and characterization of mobility in tensile and compressive stress for state-of-the-art manufacturing NMOSFETs Wang, J. -S.; Chen, William P. N.; Shih, C. -H.; Lien, C.; Su, Pin; Sheu, Y. M.; Chao, Donald Y. -S.; Goto, K.
國立交通大學 2017-04-21T06:49:05Z Evaluation of TFET and FinFET Devices and 32-Bit CLA Circuits Considering Work Function Variation and Line-Edge Roughness Chen, Chien-Ju; Chen, Yin-Nien; Fan, Ming-Long; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:49:02Z Impacts of NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:48:32Z Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFET Devices Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2017-04-21T06:48:17Z Simulation of Grain-Boundary Induced V-th Variability in Stackable NAND Flash Using a Voronoi Approach Yang, Ching-Wei; Chao, Shao-Heng; Su, Pin
國立交通大學 2016-03-28T08:17:18Z 二維材料金氧半元件於邏輯電路與記憶體應用之適用性評估(I) 蘇彬; Su Pin
國立交通大學 2016-03-28T00:04:24Z Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications Yu, Chang-Hung; Fan, Ming-Long; Yu, Kuan-Chin; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te
國立交通大學 2016-03-28T00:04:17Z Impact of Quantum Capacitance on Intrinsic Inversion Capacitance Characteristics and Inversion-Charge Loss for Multigate III-V-on-Insulator nMOSFETs Shen, Hsin-Hung; Shen, Shih-Lun; Yu, Chang-Hung; Su, Pin
國立交通大學 2015-12-02T03:00:54Z Stability/Performance Assessment of Monolithic 3D 6T/ST SRAM Cells Considering Transistor-Level Interlayer Coupling Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te
國立交通大學 2015-11-26T01:07:47Z 超薄絕緣鍺金氧半場效電晶體在量子侷限下的短通道效應模型與分析 謝欣原; Hsieh, Hsin-Yuan; 蘇彬; Su, Pin

Showing items 66-75 of 199  (20 Page(s) Totally)
<< < 2 3 4 5 6 7 8 9 10 11 > >>
View [10|25|50] records per page