English  |  正體中文  |  简体中文  |  2817115  
???header.visitor??? :  27651915    ???header.onlineuser??? :  600
???header.sponsordeclaration???
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
???ui.leftmenu.abouttair???

???ui.leftmenu.bartitle???

???index.news???

???ui.leftmenu.copyrighttitle???

???ui.leftmenu.link???

"sung min lin"???jsp.browse.items-by-author.description???

???jsp.browse.items-by-author.back???
???jsp.browse.items-by-author.order1??? ???jsp.browse.items-by-author.order2???

Showing items 1-10 of 10  (1 Page(s) Totally)
1 
View [10|25|50] records per page

Institution Date Title Author
南台科技大學 2007 64-Bit High-Speed Asynchronous Comparator Jung-Lin Yang; Wei-Peng Teng; Sung-Min Lin
南台科技大學 2006-12 Adjustable Extremely Low Power Delay Line Jung-Lin Yang; Chih-Wei Chao; Sung-Min Lin
南台科技大學 2006-11 High-Level Synthesis for Self-Timed Systems Jung-Lin Yang; Hsu-Ching Tien; Chia-Ming Hsu; Sung-Min Lin; 楊榮林;田旭清;許家銘;林嵩閔
南台科技大學 2006-11 Pseudo-DCVSL Template for Power Awarenss VLSI Circuit Design Jung-Ling Yang; Chao-Wei Huang; Sung Min Lin; Wei-Peng Deng
南台科技大學 2006-11 Swift Transition Weight Analysis for Asynchronous Finite State Jung-Lin Yang; Chih-Feng Tai; Sung-Min Lin
南台科技大學 2006-11 Tunable Delay Element for Low Power VLSI Circuit Design Jung-Lin Yang; Chih-Wei Chao; Sung-Min Lin
南台科技大學 2006 自我時序系統之高階與後端模擬平台 林嵩閔; Sung-Min Lin
南台科技大學 2005-12 HDL Modeling for Optimization and Verification of Asynchronous Controllers Jung-Lin Yang; Erik Brunvand; Sung-Min Lin
南台科技大學 2005-08 HDL Modeling for Optimization and Verification Of Extended Burst-Mode Jung-Lin Yang; Erik Brunvand; Sung-Min Lin
南台科技大學 2005-05 HDL Modeling for Burst-mode and Extended Burst-mode (BM/XBM) Asynchronous Controllers Jung-Lin Yang; Sung-Min Lin

Showing items 1-10 of 10  (1 Page(s) Totally)
1 
View [10|25|50] records per page