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"sung tze yun"
Showing items 171-195 of 195 (8 Page(s) Totally)
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| 中華大學 |
2004 |
A Memory-Efficient and High-Speed Split-radix FFT/IFFT Processor Based on Pipelined CORDIC Rotations
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
The Double Rotation CORDIC Algorithm: New Results for VLSI Implementation of Fast Sine/Cosine Generation
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
The Quantization Effects of CORDIC Arithmetic for Digital Signal Processing Applications
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
A Novel VLSI Implementation of a High-Speed CORDIC-Based Sine and Cosine Generator for OFDM Systems
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
A Low-Latency CORDIC- Based Sine and Cosine Generator for OFDM System
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
Double Rotation CORDIC: A Novel Algorithm for Fast Sine/Cosine Generation
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
A Memory-Efficient and High-Speed CORDIC-Based Split-radix FFT Processor for OFDM System
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
A Parallel-Pipelined Constant Geometry Algorithm (PCGA) for Computation of FFT on a Special Processor
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
An Efficient 8×8 2-D DCT Core Processor for Image Data Compression
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
A Cost-Effective 1024-Point FFT Processor
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
A Novel Implementation of Cost-Effective Parallel-Pipelined 8×8 DCT Processor
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
Implementation of Optimal Image Scaling Algorithm for LCD Monitor Controller
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
A Novel VLSI Implementation of 8×8 2-D DCT/IDCT Core Processor for Image Data Compression
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
An Efficient 8×8 2-D DCT /IDCT Core Processor for Image Data Compression
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
An Efficient Parallel-Pipelined Algorithm and Architecture for Computation of 2-D DCT on Two Successive Processors
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
Fast CORDIC-Based Sine/Cosine Generator Using a Double Rotation Algorithm and a Novel -prediction Algorithm
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2004 |
A Parallel-Pipelined Processor for Fast Fourier Transform
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2003 |
Image Processing Algorithms Applying on Flat Panel Display Controller
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2003 |
Chip Implementation of Image Processing Algorithms for Flat Panel Display Controller-F*Con-V.1
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2003 |
Design and Implementation Of Enriched Instruction Set 8051 Microcontroller-CH*MCU-R251
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2003 |
Chip Implementation of Optimal Image Scaling Algorithm for Flat Panel Display Controller-F*Con-V.1
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2003 |
Design and Implementation of 16-bit General Purpose Microcontroller - CH*MCU-16”
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2003 |
Implementation of Image Processing Algorithms for Flat Panel Display Using Hardware Description Language
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2003 |
Chip Implementation of Image Processing Algorithms for Flat Panel Display Controller F*Con-V.1
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2003 |
HDL Implementation of Optimal Image Scaling Algorithm for Flat Panel Display
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宋志雲; Sung, Tze-Yun |
Showing items 171-195 of 195 (8 Page(s) Totally)
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View [10|25|50] records per page
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