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Taiwan Academic Institutional Repository >
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"sung tze yun"
Showing items 96-105 of 195 (20 Page(s) Totally) << < 5 6 7 8 9 10 11 12 13 14 > >> View [10|25|50] records per page
| 中華大學 |
2006 |
Low-Power and Multiplierless Architectures for Line-Based 2-D DWT and IDWT
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
An Efficient CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphics Rendering
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
High-Efficient Architectures for 2-D Lifting-Based Forward and Inverse Discrete Wavelet Transform
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
High-Efficient Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
A High-Efficient Image Scalar Algorithm for LCD Signal Processor
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Implementation of 2-D Discrete Cosine Transform Architecture Based on CORDIC Rotation
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Implementation of CORDIC-Based Geometry Rotation for High-Speed 3-D Computer Graphic Systems
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
A High-Throughput and Memory-Efficiency 2-D DCT Architecture Based on CORDIC Rotation
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors
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宋志雲; Sung, Tze-Yun |
Showing items 96-105 of 195 (20 Page(s) Totally) << < 5 6 7 8 9 10 11 12 13 14 > >> View [10|25|50] records per page
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