|
English
|
正體中文
|
简体中文
|
Total items :0
|
|
Visitors :
51005908
Online Users :
995
Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"sung tze yun"
Showing items 126-135 of 195 (20 Page(s) Totally) << < 8 9 10 11 12 13 14 15 16 17 > >> View [10|25|50] records per page
| 中華大學 |
2006 |
Low-Power and High-Speed Architectures for 2-D DCT and IDCT Based on CORDIC Rotation
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Implementation of A High-Efficient and Cost-Effective LCD Signal Processor
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
The Closed-loop Control for Dual-Output Boost Converter with Single Inductor
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Memory-Efficient and Fast Architectures for Forward and Inverse DCT with Multiplierless Operation
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Memory-Efficient and High-Speed Split-Radix FFT/IFFT Processor Based on Pipelined CORDIC Rotations
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
A High-Efficient and Cost-Effective LCD Signal Processor
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2005 |
Design and Analysis of a High-Speed Sine/Cosine Generator in OFDM System
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2005 |
A Parallel and Pipelined Architecture for Fast Three-Dimensional Rotation Using Double Rotation CORDIC Algorithm in Graphic Engine
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2005 |
An Efficient 8×8 2-D DCT /IDCT Core Processor for Image Data Compression
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2005 |
FPGA Implementation of a High-Speed CORDIC-Based Sine and Cosine Generator for OFDM Systems
|
宋志雲; Sung, Tze-Yun |
Showing items 126-135 of 195 (20 Page(s) Totally) << < 8 9 10 11 12 13 14 15 16 17 > >> View [10|25|50] records per page
|