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机构 日期 题名 作者
中華大學 2010 A Novel VLSI Linear Array for Discrete Cosine Transform and Its Inverse 宋志雲; Sung, Tze-Yun
中華大學 2010 Folded Reconfigurable Architecture for VLSI Wavelet Filter 宋志雲; Sung, Tze-Yun
中華大學 2010 Multiplierless, Folded Reconfigurable Architecture for VLSI Wavelet Filter 宋志雲; Sung, Tze-Yun
中華大學 2010 A Novel VLSI Linear Array for 2-D DCT/IDCT 宋志雲; Sung, Tze-Yun
中華大學 2010 A Novel Linear Array for Discrete Cosine Transform 宋志雲; Sung, Tze-Yun
中華大學 2010 Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems 宋志雲; Sung, Tze-Yun
中華大學 2010 Multiplierless, Reconfigurable Folded Architecture for VLSI Wavelet Filter 宋志雲; Sung, Tze-Yun
中華大學 2010 Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter 宋志雲; Sung, Tze-Yun
中華大學 2010 An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm 宋志雲; Sung, Tze-Yun
中華大學 2010 A Novel Linear Array for Discrete Cosine Transform 宋志雲; Sung, Tze-Yun
中華大學 2010 Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter 宋志雲; Sung, Tze-Yun
國立聯合大學 2009 High-SFDR and multiplierless direct digital frequency synthesizer Sung, Tze-Yun; Hsin, Hsi-Chin; Ko, Lu-Ting
國立聯合大學 2009 Low-power and high-SFDR direct digital frequency synthesizer based on hybrid CORDIC algorithm Sung, Tze-Yun; Ko, Lyu-Ting; Hsin, Hsi-Chin
國立聯合大學 2009 Quad-tree based adaptive wavelet packet image coding Sung, Tze-Yun ; Hsin, Hsi-Chin
國立聯合大學 2009 Reconfigurable VLSI architecture for FFT processor Sung, Tze-Yun; Hsin, Hsi-Chin; Ko, Lu-Ting
國立聯合大學 2009 Context-based rate distortion estimation and its application to wavelet image coding Hsin, Hsi-Chin ; Sung, Tze-Yun
中華大學 2009 A Simple Rate Distortion Estimation for Embedded Block Coding 宋志雲; Sung, Tze-Yun
中華大學 2009 Low-Power and High-SFDR Hybrid CORDIC-Based Direct Digital Frequency Synthesizer 宋志雲; Sung, Tze-Yun
中華大學 2009 JPEG2000-Based Image Features with Its Application to Texture Segmentation 宋志雲; Sung, Tze-Yun
中華大學 2009 Low-Power and High-SFDR Direct Digital Frequency Synthesizer Based on Hybrid CORDIC Algorithm 宋志雲; Sung, Tze-Yun
中華大學 2009 Reconfigurable VLSI Architecture for FFT Processor 宋志雲; Sung, Tze-Yun
中華大學 2009 Reconfigurable VLSI Architecture for 9/7-5/3 Discrete Wavelet Transform 宋志雲; Sung, Tze-Yun
中華大學 2009 High-SFDR and Multiplierless Direct Digital Frequency Synthesizer 宋志雲; Sung, Tze-Yun
中華大學 2009 VLSI Reconfigurable Architecture for 9/7-5/3 Lifting-Based Discrete Wavelet Transform 宋志雲; Sung, Tze-Yun
中華大學 2009 Context-Based Rate Distortion Estimation and Its Application to Wavelet Image Coding 宋志雲; Sung, Tze-Yun
中華大學 2009 ㄧ種快速正弦與餘弦函數產生器 宋志雲; Sung, Tze-Yun
中華大學 2009 Quad-Tree Based Adaptive Wavelet Packet Image Coding 宋志雲; Sung, Tze-Yun
中華大學 2009 High-SFDR and Multiplierless Direct Digital Frequency Synthesizer 宋志雲; Sung, Tze-Yun
中華大學 2009 Reconfigurable VLSI Architecture for FFT Processor 宋志雲; Sung, Tze-Yun
中華大學 2008 Quad-Tree Based Adaptive Wavelet Packet Transform for Image Coding 宋志雲; Sung, Tze-Yun
中華大學 2008 VLSI Implementation of Discrete Wavelet Transform with Lifting Scheme 宋志雲; Sung, Tze-Yun
中華大學 2008 Image Coding with Adaptive Wavelet Packet Trees 宋志雲; Sung, Tze-Yun
中華大學 2008 Design of Multiplierless and High-Performance DWT and IDWT Architectures Using 4-tap Daubechies Filters 宋志雲; Sung, Tze-Yun
中華大學 2008 Adaptive Selection and Rearrangement of Wavelet Packets for Quad-Tree Image Coding 宋志雲; Sung, Tze-Yun
中華大學 2008 Image Coding with Adaptive Wavelet Packet Trees 宋志雲; Sung, Tze-Yun
中華大學 2007 A Hybrid SPIHT-EBC Image Coder 宋志雲; Sung, Tze-Yun
中華大學 2007 Memory-Efficient and High-Speed Line-Based Architecture for 2-D Discrete Wavelet Transform with Lifting Scheme 宋志雲; Sung, Tze-Yun
中華大學 2007 Low-Power and High-Performance 2-D DWT and IDWT Architectures Based on 4-tap Daubechies Filters 宋志雲; Sung, Tze-Yun
中華大學 2007 An Efficient Rearrangement of Wavelet Packet Coefficients for Embedded Quad-Tree Image Coding 宋志雲; Sung, Tze-Yun
中華大學 2007 Numerical Accuracy and Hardware Trade-Offs for Fixed-Point CORDIC Processor for Digital Signal Processing System 宋志雲; Sung, Tze-Yun
中華大學 2007 Memory-Efficient and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation 宋志雲; Sung, Tze-Yun
中華大學 2007 Memory-Efficient and High-Performance Parallel-Pipelined Architectures for 5/3 Forward and Inverse Discrete Wavelet Transform 宋志雲; Sung, Tze-Yun
中華大學 2007 VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems 宋志雲; Sung, Tze-Yun
中華大學 2007 A Hybrid Image Coder Based on SPIHT Algorithm with Embedded Block Coding 宋志雲; Sung, Tze-Yun
中華大學 2007 Fixed-Point Error Analysis of CORDIC Arithmetic for Special-Purpose Signal Processors 宋志雲; Sung, Tze-Yun
中華大學 2007 An Efficient Rearrangement of Wavelet Packet Coefficients for Embedded Image Coding Based on SPIHT Algorithm 宋志雲; Sung, Tze-Yun
中華大學 2007 Design and Simulation of Reusable IP CORDIC Core for Special-Purpose Processors 宋志雲; Sung, Tze-Yun
中華大學 2007 Memory-Efficient Multiplier-Free for 5/3 Forward and Inverse Discrete Wavelet Transform 宋志雲; Sung, Tze-Yun
中華大學 2007 Memory-EfficiEnt and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation 宋志雲; Sung, Tze-Yun
中華大學 2007 Low-Power and High-Performance 2-D DWT and IDWT Architectures Based on 4-tap Daubechies Filters 宋志雲; Sung, Tze-Yun

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