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显示项目 61-110 / 195 (共4页)
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机构	日期	题名	作者
中華大學	2009	Reconfigurable VLSI Architecture for FFT Processor	宋志雲; Sung, Tze-Yun
中華大學	2009	Reconfigurable VLSI Architecture for 9/7-5/3 Discrete Wavelet Transform	宋志雲; Sung, Tze-Yun
中華大學	2009	High-SFDR and Multiplierless Direct Digital Frequency Synthesizer	宋志雲; Sung, Tze-Yun
中華大學	2009	VLSI Reconfigurable Architecture for 9/7-5/3 Lifting-Based Discrete Wavelet Transform	宋志雲; Sung, Tze-Yun
中華大學	2009	Context-Based Rate Distortion Estimation and Its Application to Wavelet Image Coding	宋志雲; Sung, Tze-Yun
中華大學	2009	ㄧ種快速正弦與餘弦函數產生器	宋志雲; Sung, Tze-Yun
中華大學	2009	Quad-Tree Based Adaptive Wavelet Packet Image Coding	宋志雲; Sung, Tze-Yun
中華大學	2009	High-SFDR and Multiplierless Direct Digital Frequency Synthesizer	宋志雲; Sung, Tze-Yun
中華大學	2009	Reconfigurable VLSI Architecture for FFT Processor	宋志雲; Sung, Tze-Yun
中華大學	2008	Quad-Tree Based Adaptive Wavelet Packet Transform for Image Coding	宋志雲; Sung, Tze-Yun
中華大學	2008	VLSI Implementation of Discrete Wavelet Transform with Lifting Scheme	宋志雲; Sung, Tze-Yun
中華大學	2008	Image Coding with Adaptive Wavelet Packet Trees	宋志雲; Sung, Tze-Yun
中華大學	2008	Design of Multiplierless and High-Performance DWT and IDWT Architectures Using 4-tap Daubechies Filters	宋志雲; Sung, Tze-Yun
中華大學	2008	Adaptive Selection and Rearrangement of Wavelet Packets for Quad-Tree Image Coding	宋志雲; Sung, Tze-Yun
中華大學	2008	Image Coding with Adaptive Wavelet Packet Trees	宋志雲; Sung, Tze-Yun
中華大學	2007	A Hybrid SPIHT-EBC Image Coder	宋志雲; Sung, Tze-Yun
中華大學	2007	Memory-Efficient and High-Speed Line-Based Architecture for 2-D Discrete Wavelet Transform with Lifting Scheme	宋志雲; Sung, Tze-Yun
中華大學	2007	Low-Power and High-Performance 2-D DWT and IDWT Architectures Based on 4-tap Daubechies Filters	宋志雲; Sung, Tze-Yun
中華大學	2007	An Efficient Rearrangement of Wavelet Packet Coefficients for Embedded Quad-Tree Image Coding	宋志雲; Sung, Tze-Yun
中華大學	2007	Numerical Accuracy and Hardware Trade-Offs for Fixed-Point CORDIC Processor for Digital Signal Processing System	宋志雲; Sung, Tze-Yun
中華大學	2007	Memory-Efficient and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation	宋志雲; Sung, Tze-Yun
中華大學	2007	Memory-Efficient and High-Performance Parallel-Pipelined Architectures for 5/3 Forward and Inverse Discrete Wavelet Transform	宋志雲; Sung, Tze-Yun
中華大學	2007	VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems	宋志雲; Sung, Tze-Yun
中華大學	2007	A Hybrid Image Coder Based on SPIHT Algorithm with Embedded Block Coding	宋志雲; Sung, Tze-Yun
中華大學	2007	Fixed-Point Error Analysis of CORDIC Arithmetic for Special-Purpose Signal Processors	宋志雲; Sung, Tze-Yun
中華大學	2007	An Efficient Rearrangement of Wavelet Packet Coefficients for Embedded Image Coding Based on SPIHT Algorithm	宋志雲; Sung, Tze-Yun
中華大學	2007	Design and Simulation of Reusable IP CORDIC Core for Special-Purpose Processors	宋志雲; Sung, Tze-Yun
中華大學	2007	Memory-Efficient Multiplier-Free for 5/3 Forward and Inverse Discrete Wavelet Transform	宋志雲; Sung, Tze-Yun
中華大學	2007	Memory-EfficiEnt and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation	宋志雲; Sung, Tze-Yun
中華大學	2007	Low-Power and High-Performance 2-D DWT and IDWT Architectures Based on 4-tap Daubechies Filters	宋志雲; Sung, Tze-Yun
中華大學	2007	A Hybrid SPIHT-EBC Image Coder	宋志雲; Sung, Tze-Yun
中華大學	2007	Memory-EfficiEnt and High-Performance Parallel-Pipelined Architectures for 5/3 Forward and Inverse Discrete Wavelet Transform	宋志雲; Sung, Tze-Yun
中華大學	2007	An EfficiEnt RearrangemEnt of Wavelet Packet CoefficiEnts for Embedded Quad-Tree Image Coding	宋志雲; Sung, Tze-Yun
中華大學	2007	A Hybrid SPIHT-EBC Image Coder	宋志雲; Sung, Tze-Yun
中華大學	2006	High-Speed and Low-Power Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-Tap Daubechies Filters	宋志雲; Sung, Tze-Yun
中華大學	2006	Low-Power and Multiplierless Architectures for Line-Based 2-D DWT and IDWT	宋志雲; Sung, Tze-Yun
中華大學	2006	An Efficient CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphics Rendering	宋志雲; Sung, Tze-Yun
中華大學	2006	High-Efficient Architectures for 2-D Lifting-Based Forward and Inverse Discrete Wavelet Transform	宋志雲; Sung, Tze-Yun
中華大學	2006	High-Efficient Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters	宋志雲; Sung, Tze-Yun
中華大學	2006	Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters	宋志雲; Sung, Tze-Yun
中華大學	2006	A High-Efficient Image Scalar Algorithm for LCD Signal Processor	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of 2-D Discrete Cosine Transform Architecture Based on CORDIC Rotation	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of CORDIC-Based Geometry Rotation for High-Speed 3-D Computer Graphic Systems	宋志雲; Sung, Tze-Yun
中華大學	2006	A High-Throughput and Memory-Efficiency 2-D DCT Architecture Based on CORDIC Rotation	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors	宋志雲; Sung, Tze-Yun
中華大學	2006	A High-Efficient Line-Based Architecture for 2-D Lifting-Based DWT Using 9/7 Wavelet Filters	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of A High-Efficient Image Scalar Algorithm for LCD Signal Processor	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Architectures for 2-D Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters	宋志雲; Sung, Tze-Yun
中華大學	2006	Memory-Efficiency Multiplierless VLSI Architecture for 2-D DWT Using 9/7 Wavelet Filter	宋志雲; Sung, Tze-Yun
中華大學	2006	Cost-Effective Architectures for 2-D Forward and Inverse Discrete Cosine Transform Architecture	宋志雲; Sung, Tze-Yun

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