臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T15:25:59Z	Improving Capacity of Smart Grid Wireless Backhauls with Deadline Ordered Scheduler and Packet Concatenation	T.-C. Lee;Z. Tsai; T.-C. Lee; Z. Tsai; ZSEHONG TSAI
臺大學術典藏	2018-09-10T15:25:59Z	On the Capacity of Smart Grid Wireless Backhaul With Delay Guarantee and Packet Concatenation	T.-C. Lee;Z. Tsai; T.-C. Lee; Z. Tsai; ZSEHONG TSAI
臺大學術典藏	2018-09-10T15:00:41Z	A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise	P-C Huang;W-S Chang;T-C Lee; P-C Huang; W-S Chang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise	P-C Huang;W-S Chang;T-C Lee; P-C Huang; W-S Chang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth	J-A Cheng;W-S Chang;T-C Lee; J-A Cheng; W-S Chang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator	Y-H Kang;C-Y Lin;T-C Lee; Y-H Kang; C-Y Lin; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique	C-Y Lin;T-C Lee; C-Y Lin; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A 6-Gb/s Adaptive-Loop-Bandwidth Clock and Data Recovery (CDR) Circuits	L-H Chiueh;T-C Lee; L-H Chiueh; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	A Compact Multi-Input Thermoelectric Energy Harvesting System with 58.5% Power Conversion Efficiency and 32.4-mW Output Power Capability	C-L Chang;T-C Lee; C-L Chang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:41Z	Circuit for spread spectrum transmission and method thereof	T-C Lee;C-W Wong; T-C Lee; C-W Wong; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:40Z	2.4-GHz High-Efficiency Adaptive Power Harvester	C-C Lee;T-C Lee; C-C Lee; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T15:00:20Z	Improving Capacity of Smart Grid Backhauls with Deadline Ordered Scheduler and Packet Concatenation	T.-C. Lee;Z. Tsai; T.-C. Lee; Z. Tsai; ZSEHONG TSAI
臺大學術典藏	2018-09-10T09:50:53Z	A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator	C-H Wong;T-C Lee; C-H Wong; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:50:53Z	Jitter Error Cancellation Technique in Digital Domain for ADC	C-Y Lin;T-C Lee; C-Y Lin; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:50:53Z	Analysis of the Leakage Effect in a Pipelined ADC with Nanoscale CMOS Technologies	C-Y Lin Y-C Huang;T-C Lee; C-Y Lin Y-C Huang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:50:53Z	Pipelined analog-to-digital converter and method for converting analog signal to digital signal,	Y-C Huang;T-C Lee; Y-C Huang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:25:30Z	A 6-GHz All Digital PLL for Spread Spectrum Clock Generators (SSCG)	C-D Su;C-W Lee;T-C Lee; C-D Su; C-W Lee; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:25:30Z	A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter	C-C Ho;T-C Lee; C-C Ho; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	The Study of a Dual-Mode Ring Oscillator	Z-Z Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	The Design and Analysis of Dual-Delay-Path Ring Oscillators	Z-Z Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	Spilt-based Digital Background Calibration of Multistage Nonlinear Errors in Pipelined ADCS	P Zhang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	Method for achieving high-speed analog-to-digital conversion without degrading accuracy, and associated apparatus	L-H Hung; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	Digital-to-analog converter (DAC) and an associated method	T-C Lee; C-H Lin; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	Nonlinear R-2R Transistor-Only DAC	T-C Lee;C-H Lin; T-C Lee; C-H Lin; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	An Offset Phase-Locked Loop Spread Spectrum Clock Generator for SATA III	C-Y Lin;C-Y Chiang;T-C Lee; C-Y Lin; C-Y Chiang; T-C Lee; TAI-CHENG LEE

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