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Institution Date Title Author
修平科技大學 2005 Bottleneck-based heuristic dispatching rule for optimizing mixed TDD/IDD performance in various factories T.F. Ho;R. K. Li
修平科技大學 2004 Cycle time estimation with bottleneck approach for wafer fab T.F. Ho;R. K. Li
修平科技大學 2004 Heuristic dispatching rule to maximize TDD and IDD performance T.F. Ho;R. K. Li
修平科技大學 1999 Mixing macro and micro flow time estimation model:wafer fab example T.Y. Tseng;T.F. Ho;R. K. Li

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