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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T08:19:08Z	A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology	Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology	Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology	Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB	K-T Chen;T-C Lee; K-T Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:43:05Z	A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation	K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:43:05Z	A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation	K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:43:05Z	A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation	K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification	Feng-Chiu Hsieh;Tai-Cheng; Feng-Chiu Hsieh; Tai-Cheng; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits	Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits	Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits	Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:31Z	A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning	K-J Hsiao; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:37:54Z	A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning	K-J Hsiao; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:37:53Z	A Delay-Line-Based GFSK Demodulator for Low-IF Receivers	H-S Kao; M-J Yang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:03:18Z	A Spur-Suppression Technique for Phase-Locked Frequency Synthesizers	W.-L. Lee; TAI-CHENG LEE; T.-C. Lee
臺大學術典藏	2018-09-10T06:03:17Z	A Mixed-Signal GFSK Demodulator for Bluetooth	T.-C. Lee; C.-C. Chen; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:03:17Z	The design and analysis of a Miller Divider Based Clock Generator for MBOA-UWB Application	T.-C. Lee; Y.-C. Huang; TAI-CHENG LEE
臺大學術典藏	2018-09-10T06:03:17Z	The design and analysis of a DLL-Based Frequency Synthesizer for UWB Application	T.-C. Lee; K.-J. Hsiao; TAI-CHENG LEE
臺大學術典藏	2018-09-10T05:29:20Z	A Linear-Approximation Technique for Digitally-Calibrated Pipelined ADCs	D. L. Shen; T. C. Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T05:29:20Z	An Optimization Technique for RF Buffers with Active Inductors	T. C. Lee; Y. C. Huang; TAI-CHENG LEE
臺大學術典藏	2018-09-10T05:29:20Z	A DLL-Based Frequency Multiplier For MBOA-UWB System	T. C. Lee; K-J Hsiao; TAI-CHENG LEE
臺大學術典藏	2018-09-10T05:29:20Z	A Miller Divider Based Clock Generator for MBOA-UWB Application	T. C. Lee; Y. C. Huang; TAI-CHENG LEE
臺大學術典藏	2018-09-10T05:29:20Z	A Stabilization technique for phase-locked frequency synthesizers	T-C Lee; B. Razavi; TAI-CHENG LEE
臺大學術典藏	2018-09-10T04:59:51Z	6 bits 500-Ms/s Digital Self-Calibrated Pipelined Analog-to-Digital Converter	Y. H. Chen; T. C. Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T04:59:51Z	An 8-bit 2-V 2-mW 0.25-mm2 CMOS DAC	H. C. Wang; H. S. Kao; T. C. Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T03:50:57Z	A Stabilization Technique for Phase-Locked Frequency Synthesizers	TAI-CHENG LEE; B. Razavi; T. C. Lee
臺大學術典藏	2018-09-10T03:50:57Z	High-Speed CMOS Circuits for Gigabit Ethernet	T. C. Lee; TAI-CHENG LEE

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