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機構	日期	題名	作者
臺大學術典藏	2018-09-10T09:50:53Z	Pipelined analog-to-digital converter and method for converting analog signal to digital signal,	Y-C Huang;T-C Lee; Y-C Huang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:25:30Z	A 6-GHz All Digital PLL for Spread Spectrum Clock Generators (SSCG)	C-D Su;C-W Lee;T-C Lee; C-D Su; C-W Lee; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T09:25:30Z	A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter	C-C Ho;T-C Lee; C-C Ho; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	The Study of a Dual-Mode Ring Oscillator	Z-Z Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	The Design and Analysis of Dual-Delay-Path Ring Oscillators	Z-Z Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	Spilt-based Digital Background Calibration of Multistage Nonlinear Errors in Pipelined ADCS	P Zhang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	Method for achieving high-speed analog-to-digital conversion without degrading accuracy, and associated apparatus	L-H Hung; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:47:23Z	Digital-to-analog converter (DAC) and an associated method	T-C Lee; C-H Lin; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	Nonlinear R-2R Transistor-Only DAC	T-C Lee;C-H Lin; T-C Lee; C-H Lin; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques	Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques	Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques	Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	An Offset Phase-Locked Loop Spread Spectrum Clock Generator for SATA III	C-Y Lin;C-Y Chiang;T-C Lee; C-Y Lin; C-Y Chiang; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay	Y-C Hung;K Fong;T-C Lee; Y-C Hung; K Fong; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:09Z	An All‐Digital De‐skew Clock Generator for Arbitrary Wide Range Delay	K Fong;Z-Z Chen;T-C Le; K Fong; Z-Z Chen; T-C Le; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology	Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology	Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology	Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T08:19:08Z	A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB	K-T Chen;T-C Lee; K-T Chen; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:43:05Z	A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation	K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:43:05Z	A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation	K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:43:05Z	A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation	K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification	Feng-Chiu Hsieh;Tai-Cheng; Feng-Chiu Hsieh; Tai-Cheng; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits	Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE
臺大學術典藏	2018-09-10T07:09:32Z	An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits	Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE

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