| 臺大學術典藏 |
2020-06-11T06:20:58Z |
A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise
|
Huang, P.-C.;Chang, W.-S.;Lee, T.-C.; Huang, P.-C.; Chang, W.-S.; Lee, T.-C.; TAI-CHENG LEE |
| 臺大學術典藏 |
2020-06-11T06:20:57Z |
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator.
|
Kang, Yu-Hsuan;Lin, Chin-Yu;Lee, Tai-Cheng; Kang, Yu-Hsuan; Lin, Chin-Yu; Lee, Tai-Cheng; TAI-CHENG LEE |
| 臺大學術典藏 |
2020-06-11T06:20:55Z |
Few-Mode 850-nm VCSEL Chip with Direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF Link
|
Kao, H.-Y.;Tsai, C.-T.;Pong, C.-Y.;Liang, S.-F.;Weng, Z.-K.;Chi, Y.-C.;Kuo, H.-C.;Huang, J.J.;Lee, T.-C.;Shih, T.-T.;Jou, J.-J.;Cheng, W.-H.;Wu, C.-H.;Lin, G.-R.; Kao, H.-Y.; Tsai, C.-T.; Pong, C.-Y.; Liang, S.-F.; Weng, Z.-K.; Chi, Y.-C.; Kuo, H.-C.; Huang, J.J.; Lee, T.-C.; Shih, T.-T.; Jou, J.-J.; Cheng, W.-H.; Wu, C.-H.; Lin, G.-R.; TAI-CHENG LEE |
| 臺大學術典藏 |
2019-10-24T08:27:15Z |
An Energy-Efficient Self-Charged Crystal Oscillator with a Quadrature-Phase Shifter Technique
|
TAI-CHENG LEE;T-C Lee;Y-H Yang;D-N Jhou;W-S Chang; W-S Chang; D-N Jhou; Y-H Yang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2019-10-24T08:27:15Z |
An Energy-Efficient Self-Charged Crystal Oscillator with a Quadrature-Phase Shifter Technique
|
TAI-CHENG LEE;T-C Lee;Y-H Yang;D-N Jhou;W-S Chang; W-S Chang; D-N Jhou; Y-H Yang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2019-10-24T08:27:14Z |
An thermoelectric and RF multi-source energy harvesting system
|
TAI-CHENG LEE;T-C Lee;C-L Chang; C-L Chang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2019-10-24T08:27:14Z |
An thermoelectric and RF multi-source energy harvesting system
|
TAI-CHENG LEE;T-C Lee;C-L Chang; C-L Chang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2019-10-24T08:27:13Z |
A 200-MS/s Phase-Detector-Based Comparator with 400-uVrms Noise
|
TAI-CHENG LEE;T-C Lee;Y-H Wei;C-H Hsu;C-H Wong;C-Y Lin; C-Y Lin; C-H Wong; C-H Hsu; Y-H Wei; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2019-10-24T08:27:13Z |
A 200-MS/s Phase-Detector-Based Comparator with 400-uVrms Noise
|
TAI-CHENG LEE;T-C Lee;Y-H Wei;C-H Hsu;C-H Wong;C-Y Lin; C-Y Lin; C-H Wong; C-H Hsu; Y-H Wei; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2019-10-24T08:27:13Z |
A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor�VSharing Technique for Thermoelectric Energy Harvesting Applications
|
TAI-CHENG LEE;T-C Lee;C-L Chang; C-L Chang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2019-10-24T08:27:13Z |
A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor�VSharing Technique for Thermoelectric Energy Harvesting Applications
|
TAI-CHENG LEE;T-C Lee;C-L Chang; C-L Chang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:26:16Z |
An 84.7-DR Wide BW Incremental ADC
|
T-Y Wang;T-C Lee; T-Y Wang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:26:16Z |
A Single-Channel 10-b 400-MS/s 8.7-mW Pipeline ADC in a 90-nm Technology
|
C-K Hsu;T-C Lee; C-K Hsu; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise
|
P-C Huang;W-S Chang;T-C Lee; P-C Huang; W-S Chang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise
|
P-C Huang;W-S Chang;T-C Lee; P-C Huang; W-S Chang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth
|
J-A Cheng;W-S Chang;T-C Lee; J-A Cheng; W-S Chang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator
|
Y-H Kang;C-Y Lin;T-C Lee; Y-H Kang; C-Y Lin; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique
|
C-Y Lin;T-C Lee; C-Y Lin; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 6-Gb/s Adaptive-Loop-Bandwidth Clock and Data Recovery (CDR) Circuits
|
L-H Chiueh;T-C Lee; L-H Chiueh; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A Compact Multi-Input Thermoelectric Energy Harvesting System with 58.5% Power Conversion Efficiency and 32.4-mW Output Power Capability
|
C-L Chang;T-C Lee; C-L Chang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
Circuit for spread spectrum transmission and method thereof
|
T-C Lee;C-W Wong; T-C Lee; C-W Wong; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T15:00:40Z |
2.4-GHz High-Efficiency Adaptive Power Harvester
|
C-C Lee;T-C Lee; C-C Lee; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator
|
C-H Wong;T-C Lee; C-H Wong; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
Jitter Error Cancellation Technique in Digital Domain for ADC
|
C-Y Lin;T-C Lee; C-Y Lin; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
Analysis of the Leakage Effect in a Pipelined ADC with Nanoscale CMOS Technologies
|
C-Y Lin Y-C Huang;T-C Lee; C-Y Lin Y-C Huang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
Pipelined analog-to-digital converter and method for converting analog signal to digital signal,
|
Y-C Huang;T-C Lee; Y-C Huang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T09:25:30Z |
A 6-GHz All Digital PLL for Spread Spectrum Clock Generators (SSCG)
|
C-D Su;C-W Lee;T-C Lee; C-D Su; C-W Lee; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T09:25:30Z |
A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter
|
C-C Ho;T-C Lee; C-C Ho; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:47:23Z |
The Study of a Dual-Mode Ring Oscillator
|
Z-Z Chen; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:47:23Z |
The Design and Analysis of Dual-Delay-Path Ring Oscillators
|
Z-Z Chen; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:47:23Z |
Spilt-based Digital Background Calibration of Multistage Nonlinear Errors in Pipelined ADCS
|
P Zhang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:47:23Z |
Method for achieving high-speed analog-to-digital conversion without degrading accuracy, and associated apparatus
|
L-H Hung; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:47:23Z |
Digital-to-analog converter (DAC) and an associated method
|
T-C Lee; C-H Lin; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
Nonlinear R-2R Transistor-Only DAC
|
T-C Lee;C-H Lin; T-C Lee; C-H Lin; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques
|
Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques
|
Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques
|
Yen-Chuang Huang;Tai-Cheng Lee; Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
An Offset Phase-Locked Loop Spread Spectrum Clock Generator for SATA III
|
C-Y Lin;C-Y Chiang;T-C Lee; C-Y Lin; C-Y Chiang; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay
|
Y-C Hung;K Fong;T-C Lee; Y-C Hung; K Fong; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
An All‐Digital De‐skew Clock Generator for Arbitrary Wide Range Delay
|
K Fong;Z-Z Chen;T-C Le; K Fong; Z-Z Chen; T-C Le; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:08Z |
A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology
|
Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:08Z |
A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology
|
Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:08Z |
A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology
|
Yen-Chuan Huang;Tai-Cheng Lee; Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T08:19:08Z |
A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB
|
K-T Chen;T-C Lee; K-T Chen; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T07:43:05Z |
A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation
|
K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T07:43:05Z |
A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation
|
K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T07:43:05Z |
A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation
|
K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T07:09:32Z |
A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification
|
Feng-Chiu Hsieh;Tai-Cheng; Feng-Chiu Hsieh; Tai-Cheng; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T07:09:32Z |
An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits
|
Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T07:09:32Z |
An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits
|
Shih-Chun Lin;Tai-Cheng Lee; Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE |
