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| 國立交通大學 |
2017-04-21T06:49:29Z |
Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity
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Tang, Kai-Neng; Liao, Seian-Feng; Ker, Ming-Dou; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection
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Liao, Seian-Feng; Tang, Kai-Neng; Ker, Ming-Dou; Yeh, Jia-Rong; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2014-12-12T02:44:57Z |
使用低壓元件堆疊來達成高壓積體電路之靜電放電防護設計
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湯凱能; Tang, Kai-Neng; 柯明道; Ker, Ming-Dou |
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