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Institution Date Title Author
國立交通大學 2018-08-21T05:57:09Z Low-Trigger ESD Protection Design with Latch-Up Immunity for 5-V CMOS Application by Drain Engineering Chiang, Chun; Chang, Ping-Chen; Chao, Mei-Ling; Tang, Tien-Hao; Su, Kuan-Cheng; Ker, Ming-Dou
國立交通大學 2014-12-08T15:25:18Z Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology Wang, Chang-Tzu; Ker, Ming-Dou; Tang, Tien-Hao; Su, Kuan-Cheng
國立交通大學 2014-12-08T15:25:06Z ESC robustness of 40-V CMOS devices with/without drift implant Chang, Wei-Jen; Ker, Ming-Dou; Lai, Tai-Hsiang; Tang, Tien-Hao; Su, Kuan-Cheng
國立交通大學 2014-12-08T15:15:11Z Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes Ker, Ming-Dou; Wang, Chang-Tzu; Tang, Tien-Hao; Su, Kuan-Cbeng
國立交通大學 2014-12-08T15:12:36Z The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process Chang, Wei-Jen; Ker, Ming-Dou; Lai, Tai-Xiang; Tang, Tien-Hao; Su, Kuan-Cheng
義守大學 2009 Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology Wang, Chang-Tzu ; Ker, Ming-Dou ; Tang, Tien-Hao ; Su, Kuan-Cheng

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