臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
亞洲大學	1995	An Artificial Intelligent Approach to Multimedia Authoring	Timothy K. Shih
亞洲大學	1995	A Hierarchy Testing of Object-Oriented Program Structure	Chi-Ming Chung; Chun-Cha Wang; Timothy K. Shih
亞洲大學	1995	An Inheritance Level Based Metric for Object-Oriented Software Complexity,	Chi-Ming Chung; Chun-Cha Wang; Timothy K. Shih; Gwo-Ching Hsieh
亞洲大學	1995	Visualization of Logic Specification Programs	Timothy K. Shih;Rob Langsner
亞洲大學	1994-12	SPEC: A Specification Processing Environment with Controls	Timothy K. Shih ; Ruth E. Davis
亞洲大學	1994-04	A Temporal Arithmetic Based Reasoning System for Systolic Array Designs	Timothy K. Shih ; Nam Ling
亞洲大學	1994	Continuation Semantics of Logic Programs with Disciplined Exception Handling	Timothy K. Shih
亞洲大學	1993-09	Verification of Systolic Architecture Designs	Fuyau Lin ; Timothy K. Shih
亞洲大學	1993	The Use of Fixed Point Induction in Verifying Systolic Array Designs: An Applicative Approach	Nam Ling; Jonathan Huang; Timothy K. Shih
亞洲大學	1993	VSTA: A Prolog-based Formal Verifier for Systolic Array Designs	Nam Ling;Timothy K. Shih
亞洲大學	1992	A Temporal Rule-Based Expert System for Systolic Array Designs	Timothy K. Shih; Nam Ling; Xi Chen
亞洲大學	1992	Program Generation and Controls in a Specification Processing Environment,	Timothy K. Shih;Ruth Davis
亞洲大學	1992	The Specification and Verification of Synchronous Concurrent Computation	Fuyau Lin; Timothy K. Shih; Huanchau Lin; Hsiren Wang
亞洲大學	1992	A Specification Processing Environment for Making Well Engineered Logic Programs	Timothy K. Shih; Ruth Davis; Rob Langsner
亞洲大學	1992	Intelligence Backtracking and Controls Based on a Deduction Status Representation in Logic Programming	Timothy K. Shih;Ruth Davis
亞洲大學	1992	Verification of Systolic Architecture Designs	Fuyau Lin;Timothy K. Shih
亞洲大學	1992	Inductive Techniques for Formal Verification of Systolic Array Designs in DSP Applications	Nam Ling; Timothy K. Shih; Jonathan Huang
亞洲大學	1992	Using Prolog as a Tool for Systolic Array Designs	Fuyau Lin; Timothy K. Shih; Nam Lin; Ruth Davis
亞洲大學	1992	Disciplined Exceptions in Logic Programming,	Timothy K. Shih; Ruth E. Davis; Fuyau Lin
亞洲大學	1992	An Automatic Design Specification and Verification Tool for Systolic Architecture	Timothy K. Shih; Nam Ling; Ruth Davis; Fuyau Lin
亞洲大學	1991	Verification Tools for Systolic Array Design	Fuyau Lin; Timothy K. Shih; Nam Ling
亞洲大學	1991	Axiomatic Approach for Systolic Array Design	Fuyau Lin; Timothy K. Shih;Nam Ling
亞洲大學	1991	Automatic Formal Verification of Systolic Array Designs	Nam Ling; Fuyau Lin; Timothy K. Shih;Ruth Davis
亞洲大學	1990	A CASE for Logic Programming	R. E. Davis;Timothy K. Shih

Showing items 366-389 of 389 (8 Page(s) Totally)
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