|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"tsai chia chun"
Showing items 51-68 of 68 (3 Page(s) Totally)
<< < 1 2 3
View [10|25|50] records per page
| 臺大學術典藏 |
2007-04-19T04:37:35Z |
GEAR: a general area router using planning approach
|
Hu, Yu-Hen; Tsai, Chia-Chun; Chen, Sao-Jie; Chen, Yuh-Lin; Hu, Yu-Hen;Tsai, Chia-Chun;Chen, Yuh-Lin;Chen, Sao-Jie |
| 東吳大學 |
2007 |
影響品牌延伸成功因素之實證研究---以數位相機為例
|
蔡佳純; Tsai, Chia Chun |
| 國立臺灣大學 |
2006-05 |
Inductance extraction for general interconnect structures
|
Lai, Chun-Ying; Jeng, Shyh-Kang; Chang, Yao-Wen; Tsai, Chia-Chun |
| 臺大學術典藏 |
2006-05 |
Inductance extraction for general interconnect structures
|
Lai, Chun-Ying; Jeng, Shyh-Kang; Chang, Yao-Wen; Tsai, Chia-Chun; Lai, Chun-Ying; Jeng, Shyh-Kang; Chang, Yao-Wen; Tsai, Chia-Chun |
| 元培科技大學 |
2003-04-01 |
Appraisal of stress and ways of coping reported by associate degree nursing students in relation to the pediatric clinical experience in Taiwan, R.O.C.
|
Tsai, Chia-Chun |
| 東海大學 |
2003 |
鉑或鈀修飾中孔型分子篩之催化氫化反應
|
蔡佳純; Tsai, Chia-Chun |
| 國立臺灣大學 |
2000 |
Efficient routability check algorithms for segmented channel routing
|
Yang, Cheng-Hsing; Chen, Sao-Jie; Ho, Jan-Ming; Tsai, Chia-Chun |
| 國立臺灣大學 |
1999-10 |
An even wiring approach to the ball grid array package routing
|
Chen, Shuenn-Shi; Chen, Jong-Jang; Tsai, Chia-Chun; Chen, Sao-Jie |
| 臺大學術典藏 |
1999-10 |
An even wiring approach to the ball grid array package routing
|
Chen, Shuenn-Shi; Chen, Jong-Jang; Tsai, Chia-Chun; Chen, Sao-Jie; Chen, Shuenn-Shi; Chen, Jong-Jang; Tsai, Chia-Chun; Chen, Sao-Jie |
| 國立臺灣大學 |
1999-01 |
An automatic router for the pin grid array package
|
Chen, Shuenn-Shi; Chen, Jong-Jang; Chen, Sao-Jie; Tsai, Chia-Chun |
| 國立臺灣大學 |
1999-01 |
An efficient two-level partitioning algorithm for VLSI circuits
|
Cherng, Jong-Sheng; Chen, Soo-Jie; Tsai, Chia-Chun; Ho, Jan-Ming |
| 臺大學術典藏 |
1999-01 |
An automatic router for the pin grid array package
|
Chen, Shuenn-Shi; Chen, Jong-Jang; Chen, Sao-Jie; Tsai, Chia-Chun; Chen, Shuenn-Shi; Chen, Jong-Jang; Chen, Sao-Jie; Tsai, Chia-Chun |
| 國立臺灣大學 |
1999 |
A New Approach to the Ball Grid Array Package Routing
|
Chen, Shuenn-Shi; Chen, Jong-Jang; Lee, Trong-Yen; Tsai, Chia-Chun; Chen, Sao-Jie |
| 國立臺灣大學 |
1995-06 |
One-phase technology mapping for EPGAs using extended GBDD hash tables
|
Yang, Cheng-Hsing; Chen, Sao-Jie; Ho, Jan-Ming; Tsai, Chia-Chun |
| 國立臺灣大學 |
1995-05 |
An efficient approach for via minimization in multi-layer VLSI/PCB routing
|
Cherng, Jong-Sheng; Chen, Sao-Jie; Tsai, Chia-Chun; Ho, Jan-Ming |
| 國立臺灣大學 |
1991-05 |
Hybrid routing on multichip modules
|
Tsai, Chia-Chun; Chen, Sao-Jie; Hsiao, Pei-Yung; Feng, Wu-Shiung |
| 國立臺灣大學 |
1991-05 |
GEAR: a general area router using planning approach
|
Chen, Yuh-Lin; Chen, Sao-Jie; Tsai, Chia-Chun; Hu, Yu-Hen |
| 國立臺灣大學 |
1990 |
Generalized terminal connectivity problem for multilayer layout scheme
|
Tsai, Chia-Chun; Chen, Sao-Jie; Feng, Wu-Shiung |
Showing items 51-68 of 68 (3 Page(s) Totally)
<< < 1 2 3
View [10|25|50] records per page
|
