English  |  正體中文  |  简体中文  |  总笔数 :2831195  
造访人次 :  33225551    在线人数 :  1056
教育部委托研究计画      计画执行:国立台湾大学图书馆
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
关于TAIR

浏览

消息

著作权

相关连结

"tsai fu yi"的相关文件

回到依作者浏览
依题名排序 依日期排序

显示项目 1-9 / 9 (共1页)
1 
每页显示[10|25|50]项目

机构 日期 题名 作者
國立交通大學 2017-04-21T06:49:33Z On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process Ker, Ming-Dou; Chiu, Po-Yen; Tsai, Fu-Yi; Chang, Yeong-Jar
國立交通大學 2014-12-08T15:36:36Z Electrooptical Properties of InGaAs/GaAs Strained Single Quantum Wells Lu, Chien-Rong; Lou, Shry-Fong; Cheng, Hung-Hsiang; Lee, Chien-Ping; Tsai, Fu-Yi
國立交通大學 2014-12-08T15:28:41Z Failure Analysis on Gate-Driven ESD Clamp Circuit after TLP Stresses of Different Voltage Steps in a 16-V CMOS Process Dai, Chia-Tsen; Chiu, Po-Yen; Ker, Ming-Dou; Tsai, Fu-Yi; Peng, Yan-Hua; Tsai, Chia-Ku
國立交通大學 2014-12-08T15:25:20Z Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process Chiu, Po-Yen; Ker, Ming-Dou; Tsai, Fu-Yi; Chang, Yeong-Jar
臺北醫學大學 2011 Effect of collagen on the mechanical properties of hydroxyapatite coatings Ou, Keng-Liang;Chungc, Ren-Jei;Tsai, Fu-Yi;Liang, Pei-Yu;Huang, Shih-Wei;Chang, Shou-Yi
義守大學 2009 Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process Chiu, Po-Yen ; Ker, Ming-Dou ; Tsai, Fu-Yi ; Chang, Yeong-Jar
義守大學 2009 On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process Ker, Ming-Dou ; Chiu, Po-Yen ; Tsai, Fu-Yi ; Chang, Yeong-Jar
國立成功大學 2001 InGaAs/GaAs quantum wells and quantum dots on (111)B orientation Tyan, Shing-Long; Lin, Yun-Ging; Tsai, Fu-Yi; Lee, Chien-Ping; Shields, Philip A.; Nicholas, Robin J.
國立成功大學 2000-06 Magneto-photoluminescence study of InGaAs/GaAs quantum wells and quantum dots grown on (111)B GaAs substrate Tyan, Shing-Long; Shields, Philip A.; Nicholas, Robin J.; Tsai, Fu-Yi; Lee, Chien-Ping

显示项目 1-9 / 9 (共1页)
1 
每页显示[10|25|50]项目