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| 國立交通大學 |
2018-08-21T05:53:00Z |
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures
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Wang, Po-Hao; Chien, Yung-Chen; Tsai, Shang-Jen; Lin, Xuan-Yu; Tanjung, Rizal; Lin, Yi-Sian; Syu, Shu-Wei; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu |
| 國立交通大學 |
2017-04-21T06:56:22Z |
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors
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Wang, Po-Hao; Tsai, Shang-Jen; Tanjung, Rizal; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu |
| 國立交通大學 |
2017-04-21T06:48:46Z |
A Latency-Elastic and Fault-Tolerant Cache for Improving Performance and Reliability on Low Voltage Operation
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Yu, Yung-Hui; Wang, Po-Han; Tsai, Shang-Jen; Chen, Tien-Fu |
| 國立交通大學 |
2015-11-26T00:56:29Z |
用於非對稱式處理器系統之可同盟字元線快取記憶體以暫時性效能提升
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蔡上仁; Tsai, Shang-Jen; 陳添福; Chen, Tien-Fu |
Showing items 1-4 of 4 (1 Page(s) Totally)
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