臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T06:21:51Z	GOAL: A graphical tool for manipulating Büchi automata and temporal formulae	Tsay, Y.-K.;Chen, Y.-F.;Tsai, M.-H.;Wu, K.-N.;Chan, W.-C.; Tsay, Y.-K.; Chen, Y.-F.; Tsai, M.-H.; Wu, K.-N.; Chan, W.-C.; YIH-KUEN TSAY
臺大學術典藏	2018-09-10T06:21:51Z	Automated technology for verification and analysis (ATVA 2005): Preface	Peled, D.A.;Tsay, Y.-K.; Peled, D.A.; Tsay, Y.-K.; YIH-KUEN TSAY
臺大學術典藏	2018-09-10T05:16:55Z	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface	Peled, D.A.;Tsay, Y.-K.; Peled, D.A.; Tsay, Y.-K.; YIH-KUEN TSAY
臺大學術典藏	2018-09-10T04:48:18Z	Fault-Tolerant Algorithms for Fair Interprocess Synchronization	Tsay, Y.-K.;Bagrodia, R.L.; Tsay, Y.-K.; Bagrodia, R.L.; YIH-KUEN TSAY
臺大學術典藏	2018-09-10T04:28:32Z	Composing temporal-logic specifications with machine assistance	Teng, J.-W.;Tsay, Y.-K.; Teng, J.-W.; Tsay, Y.-K.; YIH-KUEN TSAY
臺大學術典藏	2018-09-10T04:28:32Z	Some impossibility results in interprocess synchronization	Tsay, Y.-K.;Bagrodia, R.L.; Tsay, Y.-K.; Bagrodia, R.L.; YIH-KUEN TSAY
臺大學術典藏	2018-09-10T03:26:28Z	Compositional verification in linear-time temporal logic	Tsay, Y.-K.; Tsay, Y.-K.; YIH-KUEN TSAY
臺大學術典藏	2018-09-10T03:26:28Z	Algorithmic analysis of programs with well quasi-ordered domains	Abdulla, P.A.;?erans, K.;Jonsson, B.;Tsay, Y.-K.; Abdulla, P.A.; ?erans, K.; Jonsson, B.; Tsay, Y.-K.; YIH-KUEN TSAY
國立臺灣大學	2009-08	Automated Compositional Reasoning of Intuitionistically Closed Regular Properties	Tsay, Y.-K.; Wang, B.-Y.
國立臺灣大學	2009-05	Tool Support for Learning Buchi Automata and Linear Temporal Logic	Tsay, Y. -K.; Chen, Y. -F.; Tsai, M. -H.; Wu, K. -N.; Chan, W. -C.; Luo, C. -J.; Chang, J. -S.
國立臺灣大學	2007-02	Automated Technology for Verification and Analysis (ATVA 2005) - Preface	Peled, D. A.; Tsay, Y. -K.
國立臺灣大學	2000	Algorithmic Analysis of Programs with Well Quasi-Ordered Domains	Abdulla, P. A.; Cerans, K.; Jonsson, B.; Tsay, Y.K.
國立臺灣大學	1996-10	Assumption/Guarantee Specifications in Linear-Time Temporal Logic	Jonsson, B.; Tsay, Y. -K.
國立臺灣大學	1995-01	Deducing Fairness Properties in UNITY Logic - A New Completeness Result	Tsay,Y. -K.; Bagrodia, R. L.
臺大學術典藏	1995	Assumption/guarantee specifications in linear-time temporal logic	Jonsson, B; Tsay, Y.-K.; YIH-KUEN TSAY; Jonsson, B;Tsay, Y.-K.
國立臺灣大學	1994-07	Fault-Tolerant Algorithms for Fair Interprocess Synchronization	Tsay, Y.-K.; Bagrodia, R. L.
國立臺灣大學	1993-07	Some Impossibility Results in Interprocess Synchronization	Tsay,Y. -K.; Bagrodia, R. L.
臺大學術典藏	1992	A real-time algorithm for fair interprocess synchronization	Tsay, Y.-K;Bagrodia, R.L.; Tsay, Y.-K; Bagrodia, R.L.; YIH-KUEN TSAY

Showing items 21-38 of 38 (2 Page(s) Totally)
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