| 臺大學術典藏 |
2018-09-10T06:20:23Z |
Reconfigurable architecture for video applications
|
Lian Jr.; C.; Tseng, P.-C.; Chen, T.-C.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:50:33Z |
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications
|
Lin, C.-P.; Tseng, P.-C.; Chiu, Y.-T.; Lin, S.-S.; Cheng, C.-C.; Fang, H.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
Advances in hardware architectures for image and video coding - A survey
|
Tseng, P.-C.; Chang, Y.-C.; Huang, Y.-W.; Fang, H.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Nearly lossless content-dependent low-power DCT design for mobile video applications
|
Lin, C.-P.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Multiple-lifting Scheme: Memory-efficient VLSI implementation for line-based 2-D DWT
|
Cheng, C.-C.; Huang, C.-T.; Tseng, P.-C.; Pan, C.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Multi-mode embedded compression codec engine for power-aware video coding system
|
Cheng, C.-C.; Tseng, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:45Z |
Reconfigurable discrete wavelet transform processor for heterogeneous reconfigurable multimedia systems
|
Tseng, P.-C.;Huang, C.-T.;Chen, L.-G.; Tseng, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:44Z |
VLSI architecture for forward discrete wavelet transform based on B-spline factorization
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:44Z |
VLSI architecture for fifting-based shape-adaptive discrete wavelet transform with odd-symmetric filters
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:23Z |
81MS/s JPEG2000 single-chip encoder with rate-distortion optimization
|
Fang, H.-C.; Huang, C.-T.; Chang, Y.-W.; Wang, T.-C.; Tseng, P.-C.; Lian, C.-J.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:22Z |
B-spline factorization-based architecture for inverse discrete wavelet transform
|
Huang, C.-T.;Tseng, P.-C.;Chen, L.-G.; Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:21Z |
Flipping Structure: An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:20Z |
Hardware architecture design for visual processing: Present and future
|
Tseng, P.-C.; Chen, L.-G.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:18Z |
Multi-mode content-aware motion estimation algorithm for power-aware video coding systems
|
Lin, S.-S.;Tseng, P.-C.;Lin, C.-P.;Chen, L.-G.; Lin, S.-S.; Tseng, P.-C.; Lin, C.-P.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:18Z |
Memory analysis and architecture for two-dimensional discrete wavelet transform
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:18Z |
Low-power parallel tree architecture for full search block-matching motion estimation
|
Lin, S.-S.; Tseng, P.-C.; Chen, L.-G.; Lin, S.-S.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:17Z |
Reconfigurable discrete cosine transform processor for object-based video signal processing
|
Tseng, P.-C.; Haung, C.-T.; Chen, L.-G.; LIANG-GEE CHEN; Tseng, P.-C.; Haung, C.-T.; Chen, L.-G. |
| 臺大學術典藏 |
2018-09-10T04:27:48Z |
81MS/s JPEG 2000 single-chip encoder with rate-distortion optimization
|
Fang, H.-C.; Huang, C.-T.; Chang, Y.-W.; Wang, T.-C.; Tseng, P.-C.; Lian, C.-J.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:43Z |
Reconfigurable discrete wavelet transform architecture for advanced multimedia systems
|
LIANG-GEE CHEN; Chen, L.-G.; Huang, C.-T.; Tseng, P.-C. |
| 臺大學術典藏 |
2018-09-10T04:27:42Z |
VLSI architecture for discrete wavelet transform based on B-spline factorization
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:54Z |
A digital signal processor with programmable correlator array architecture for third generation wireless communication system
|
Chen, C.-K.; Tseng, P.-C.; Chang, Y.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:51Z |
VLSI implementation of shape-adaptive discrete wavelet transform
|
Tseng, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T03:43:44Z |
CDSP: An application-specific digital signal processor for third generation wireless communications
|
Tseng, P.-C.; Chen, C.-K.; Chen, L.-G.; LIANG-GEE CHEN |
