| 臺大學術典藏 |
2018-07-06T13:43:05Z |
Memory analysis and architecture for two-dimensional discrete wavelet transform
|
Chen, Liang-Gee; Tseng, Po-Chih; Huang, Chao-Tsung; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2015 |
利用奈米薄膜及活性碳吸附去除水中Trimethoprim、Sulfamethoxazole與Bisphenol-A
|
曾渤之; Tseng, Po-Chih |
| 國立臺灣大學 |
2007 |
Power-Aware Multimedia: Concepts and Design Perspectives
|
Lian, Chung-Jr; Chien, Shao-Yi; Lin, Chia-ping; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2005-11 |
Multi-mode embedded compression codec engine for power-aware video coding system
|
Cheng, Chih-Chi; Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee |
| 國立臺灣大學 |
2005-05 |
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT
|
Cheng, Chih-Chi; Huang, Chao-Tsung; Tseng, Po-Chih; Pan, Chia-Ho; Chen, Liang-Gee |
| 國立臺灣大學 |
2005-04 |
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2005-04 |
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2005 |
具功率感知的視訊編解碼器系統之設計與實現
|
曾博志; Tseng, Po-Chih |
| 國立臺灣大學 |
2005 |
Advances in Hardware Architectures for Image and Video Coding—A Survey
|
Tseng, Po-Chih; Chang, Yung-Chi; Huang, Yu-Wen; Fang, Hung-Chi; Huang, Chao-Tsung; Chen, Liang-Gee |
| 國立臺灣大學 |
2005 |
VLSI Architecture for Lifting-based Shape-Adaptive Discrete Wavelet Transform with Odd-symmetric Filters
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2005 |
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2005 |
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2005 |
Reconfigurable discrete wavelet transform processor for heterogeneous reconfigurable multimedia systems
|
Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee |
| 國立臺灣大學 |
2005 |
Reconfigurable motion estimator for power-aware video coding systems
|
Chien, Shao-Yi; Lin, Chia-Ping; Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2005 |
Reconfigurable motion estimator for power-aware video coding systems
|
Chien, Shao-Yi; Lin, Chia-Ping; Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee; Chien, Shao-Yi; Lin, Chia-Ping; Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-08 |
Hardware architecture design for visual processing: present and future
|
Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2004-08 |
Hardware architecture design for visual processing: present and future
|
Tseng, Po-Chih; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Reconfigurable discrete cosine transform processor for object-based video signal processing
|
Tseng, Po-Chih; Haung, Chao-Tsung; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
B-spline factorization-based architecture for inverse discrete wavelet transform
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Memory analysis and architecture for two-dimensional discrete wavelet transform
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Low-power parallel tree architecture for full search block-matching motion estimation
|
Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2004-05 |
Reconfigurable discrete cosine transform processor for object-based video signal processing
|
Tseng, Po-Chih; Haung, Chao-Tsung; Chen, Liang-Gee; Tseng, Po-Chih; Haung, Chao-Tsung; Chen, Liang-Gee |
| 臺大學術典藏 |
2004-05 |
B-spline factorization-based architecture for inverse discrete wavelet transform
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2004-05 |
Low-power parallel tree architecture for full search block-matching motion estimation
|
Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee; Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-02 |
81MS/s JPEG2000 single-chip encoder with rate-distortion optimization
|
Fang, Hung-Chi; Huang, Chao-Tsung; Chang, Yu-Wei; Wang, Tu-Chih; Tseng, Po-Chih; Lian, Chung-Jr; Chen, Liang-Gee |
| 臺大學術典藏 |
2004-02 |
81MS/s JPEG2000 single-chip encoder with rate-distortion optimization
|
Fang, Hung-Chi; Huang, Chao-Tsung; Chang, Yu-Wei; Wang, Tu-Chih; Tseng, Po-Chih; Lian, Chung-Jr; Chen, Liang-Gee; Fang, Hung-Chi; Huang, Chao-Tsung; Chang, Yu-Wei; Wang, Tu-Chih; Tseng, Po-Chih; Lian, Chung-Jr; Chen, Liang-Gee |
| 國立臺灣大學 |
2004 |
Multi-mode content-aware motion estimation algorithm for power-aware video coding systems
|
Lin, Siou-Shen; Tseng, Po-Chih; Lin, Chia-Ping; Chen, Liang-Gee |
| 國立臺灣大學 |
2004 |
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2004 |
Multi-mode content-aware motion estimation algorithm for power-aware video coding systems
|
Lin, Siou-Shen; Tseng, Po-Chih; Lin, Chia-Ping; Chen, Liang-Gee; Lin, Siou-Shen; Tseng, Po-Chih; Lin, Chia-Ping; Chen, Liang-Gee |
| 國立臺灣大學 |
2003-09 |
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2003-09 |
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2003-08 |
Perspectives of multimedia SoC
|
Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2003-08 |
VLSI architecture for discrete wavelet transform based on B-spline factorization
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2003-08 |
Reconfigurable discrete wavelet transform architecture for advanced multimedia systems
|
Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee |
| 臺大學術典藏 |
2003-08 |
Perspectives of multimedia SoC
|
Tseng, Po-Chih; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2003-08 |
VLSI architecture for discrete wavelet transform based on B-spline factorization
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2003-08 |
Reconfigurable discrete wavelet transform architecture for advanced multimedia systems
|
Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee; Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee |
| 國立臺灣大學 |
2002-10 |
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2002-10 |
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method
|
Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee |
| 臺大學術典藏 |
2002-10 |
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2002-10 |
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method
|
Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee; Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee |
| 國立臺灣大學 |
2002-05 |
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2002-05 |
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2001-06 |
CDSP: an application-specific digital signal processor for third generation wireless communications
|
Tseng, Po-Chih; Chen, Chi-Kuang; Chen, Liang-Gee |
| 國立臺灣大學 |
2001-06 |
H.26L intra mode encoder architecture for digital camera application
|
Wang, Tu-Chih; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2001-06 |
CDSP: an application-specific digital signal processor for third generation wireless communications
|
Tseng, Po-Chih; Chen, Chi-Kuang; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Chi-Kuang; Chen, Liang-Gee |
| 臺大學術典藏 |
2001-06 |
H.26L intra mode encoder architecture for digital camera application
|
Chen, Liang-Gee; Tseng, Po-Chih; Wang, Tu-Chih; Wang, Tu-Chih; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2001 |
A digital signal processor with programmable correlator arrayarchitecture for third generation wireless communication system
|
Chen, Chi-Kuang; Tseng, Po-Chih; Chang, Yung-Chil; Chen, Liang-Gee |
