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機構	日期	題名	作者
國立臺灣大學	2004-08	Hardware architecture design for visual processing: present and future	Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2004-08	Hardware architecture design for visual processing: present and future	Tseng, Po-Chih; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2004-05	Reconfigurable discrete cosine transform processor for object-based video signal processing	Tseng, Po-Chih; Haung, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2004-05	B-spline factorization-based architecture for inverse discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2004-05	Memory analysis and architecture for two-dimensional discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2004-05	Low-power parallel tree architecture for full search block-matching motion estimation	Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2004-05	Reconfigurable discrete cosine transform processor for object-based video signal processing	Tseng, Po-Chih; Haung, Chao-Tsung; Chen, Liang-Gee; Tseng, Po-Chih; Haung, Chao-Tsung; Chen, Liang-Gee
臺大學術典藏	2004-05	B-spline factorization-based architecture for inverse discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2004-05	Low-power parallel tree architecture for full search block-matching motion estimation	Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee; Lin, Siou-Shen; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2004-02	81MS/s JPEG2000 single-chip encoder with rate-distortion optimization	Fang, Hung-Chi; Huang, Chao-Tsung; Chang, Yu-Wei; Wang, Tu-Chih; Tseng, Po-Chih; Lian, Chung-Jr; Chen, Liang-Gee
臺大學術典藏	2004-02	81MS/s JPEG2000 single-chip encoder with rate-distortion optimization	Fang, Hung-Chi; Huang, Chao-Tsung; Chang, Yu-Wei; Wang, Tu-Chih; Tseng, Po-Chih; Lian, Chung-Jr; Chen, Liang-Gee; Fang, Hung-Chi; Huang, Chao-Tsung; Chang, Yu-Wei; Wang, Tu-Chih; Tseng, Po-Chih; Lian, Chung-Jr; Chen, Liang-Gee
國立臺灣大學	2004	Multi-mode content-aware motion estimation algorithm for power-aware video coding systems	Lin, Siou-Shen; Tseng, Po-Chih; Lin, Chia-Ping; Chen, Liang-Gee
國立臺灣大學	2004	Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2004	Multi-mode content-aware motion estimation algorithm for power-aware video coding systems	Lin, Siou-Shen; Tseng, Po-Chih; Lin, Chia-Ping; Chen, Liang-Gee; Lin, Siou-Shen; Tseng, Po-Chih; Lin, Chia-Ping; Chen, Liang-Gee
國立臺灣大學	2003-09	Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2003-09	Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2003-08	Perspectives of multimedia SoC	Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2003-08	VLSI architecture for discrete wavelet transform based on B-spline factorization	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2003-08	Reconfigurable discrete wavelet transform architecture for advanced multimedia systems	Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
臺大學術典藏	2003-08	Perspectives of multimedia SoC	Tseng, Po-Chih; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2003-08	VLSI architecture for discrete wavelet transform based on B-spline factorization	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2003-08	Reconfigurable discrete wavelet transform architecture for advanced multimedia systems	Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee; Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2002-10	Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2002-10	Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method	Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
臺大學術典藏	2002-10	Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2002-10	Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method	Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee; Tseng, Po-Chih; Huang, Chao-Tsung; Chen, Liang-Gee
國立臺灣大學	2002-05	Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2002-05	Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method	Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2001-06	CDSP: an application-specific digital signal processor for third generation wireless communications	Tseng, Po-Chih; Chen, Chi-Kuang; Chen, Liang-Gee
國立臺灣大學	2001-06	H.26L intra mode encoder architecture for digital camera application	Wang, Tu-Chih; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏	2001-06	CDSP: an application-specific digital signal processor for third generation wireless communications	Tseng, Po-Chih; Chen, Chi-Kuang; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Chi-Kuang; Chen, Liang-Gee
臺大學術典藏	2001-06	H.26L intra mode encoder architecture for digital camera application	Chen, Liang-Gee; Tseng, Po-Chih; Wang, Tu-Chih; Wang, Tu-Chih; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學	2001	A digital signal processor with programmable correlator arrayarchitecture for third generation wireless communication system	Chen, Chi-Kuang; Tseng, Po-Chih; Chang, Yung-Chil; Chen, Liang-Gee

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	造訪人次 : 50952253 線上人數 : 797 教育部委託研究計畫計畫執行:國立臺灣大學圖書館