| 國立交通大學 |
2019-04-02T05:58:59Z |
Effect of Ion-Implantation Temperature on Contact Resistance of Metal/n-Type 4H-SiC With Ar Plasma Treatment
|
Tsui, Bing-Yue; Cheng, Jung-Chien |
| 國立交通大學 |
2019-04-02T05:58:38Z |
Effects of Rapid Thermal Annealing on Ar Inductively Coupled Plasma-Treated n-Type 4H-SiC Schottky and Ohmic Contacts
|
Cheng, Jung-Chien; Tsui, Bing-Yue |
| 國立交通大學 |
2019-04-02T05:58:10Z |
A High-Performance 30-nm Gate-All-Around Poly-Si Nanowire Thin-Film Transistor With NH3 Plasma Treatment
|
Lee, Chen-Ming; Tsui, Bing-Yue |
| 國立交通大學 |
2018-08-21T05:57:09Z |
A Comprehensive Evaluation of the Performance of Fin-type Epitaxial Tunnel Layer (ETL) Tunnel FET
|
Lin, Po-Shao; Tsui, Bing-Yue |
| 國立交通大學 |
2018-08-21T05:57:09Z |
Effects of Vanadium Incorporation on the Electron Schottky Barrier Height Reduction of NiGe/Ge
|
Chen, Yi-Ju; Tsui, Bing-Yue |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Scaling of Gate Dielectric on Ge Substrate
|
Chan, Yung-Hsiang; Tsui, Bing-Yue |
| 國立交通大學 |
2018-08-21T05:56:34Z |
Modeling the Variability Caused by Random Grain Boundary and Trap-location Induced Asymmetrical Read Behavior for a Tight-pitch Vertical Gate 3D NAND Flash Memory Using Double-Gate Thin-Film Transistor (TFT) Device
|
Hsiao, Yi-Hsuan; Lue, Hang-Ting; Chen, Wei-Chen; Chen, Chih-Ping; Chang, Kuo-Ping; Shih, Yen-Hao; Tsui, Bing-Yue; Lu, Chih-Yuan |
| 國立交通大學 |
2018-08-21T05:54:27Z |
Reduced Junction Leakage by Hot Phosphorus Ion Implantation of NiGe-Contacted Germanium n(+)/p Shallow Junction
|
Chen, Yi-Ju; Tsui, Bing-Yue; Chou, Hung-Ju; Li, Ching-I; Lin, Ger-Pin; Hu, Shao-Yu |
| 國立交通大學 |
2018-08-21T05:54:09Z |
Strong Fermi-level pinning induced by argon inductively coupled plasma treatment and post-metal deposition annealing on 4H-SiC
|
Tsui, Bing-Yue; Cheng, Jung-Chien; Yen, Cheng-Tyng; Lee, Chawn-Ying |
| 國立交通大學 |
2018-08-21T05:54:04Z |
Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation
|
Tseng, Yuan-Hung; Lin, Chung-Yu; Tsui, Bing-Yue |
| 國立交通大學 |
2018-08-21T05:53:52Z |
Bandgap engineering of Si1-xGex epitaxial tunnel layer for tunnel FETs
|
Chen, Yi-Ju; Tsui, Bing-Yue |
| 國立交通大學 |
2018-08-21T05:53:02Z |
Reduction of Specific Contact Resistance on n-Type Implanted 4H-SiC Through Argon Inductively Coupled Plasma Treatment and Post-Metal Deposition Annealing
|
Cheng, Jung-Chien; Tsui, Bing-Yue |
| 國立交通大學 |
2018-01-24T07:42:47Z |
以二氧化鋯作為閘極介電層之鍺金屬-氧化層-半導體電容器與N型金屬-氧化層-半導體電晶體之閘極工程研究
|
詹詠翔; 崔秉鉞; Chan, Yung-Hsiang; Tsui, Bing-Yue |
| 國立交通大學 |
2018-01-24T07:42:25Z |
熱製程對鍺金屬絕緣層半導體元件上閘極介電質品質影響之研究
|
危爾捷; 崔秉鉞; 吳品鈞; Wei, Erh-Jye; Tsui, Bing-Yue; Wu, Pin-Jiun |
| 國立交通大學 |
2018-01-24T07:39:09Z |
4H型碳化矽溝槽式閘極金氧半場效功率電晶體之關鍵製程研究
|
曾元宏; 崔秉鉞; Tseng, Yuan-Hung; Tsui, Bing-Yue |
| 國立交通大學 |
2018-01-24T07:39:06Z |
鰭狀磊晶穿隧層穿隧電晶體之性能評估及n型磊晶穿隧層穿隧電晶體性能改善之研究
|
林柏劭; 崔秉鉞; Lin, Po-Shao; Tsui, Bing-Yue |
| 國立交通大學 |
2018-01-24T07:39:06Z |
氮化矽逆向梯形波導耦合器之設計、製作與量測
|
林劭恩; 崔秉鉞; 陳瓊華; Lin, Shao-En; Tsui, Bing-Yue; Chen, Chyong-Hua |
| 國立交通大學 |
2018-01-24T07:39:06Z |
晶粒結構對於平面與垂直閘極半導體-氧化矽-氮化矽-氧化矽-半導體記憶體寫入速度的影響
|
常瑋軒; 崔秉鉞; Chang, Wei-Hsuan; Tsui, Bing-Yue |
| 國立交通大學 |
2018-01-24T07:38:48Z |
以離子植入選擇性增加碳化矽氧化速率暨溝槽式接面位障蕭基二極體之研究
|
林忠佑; 崔秉鉞; Lin, Chung-Yu; Tsui, Bing-Yue |
| 國立交通大學 |
2018-01-24T07:38:25Z |
磊晶穿隧層穿隧電晶體之研究
|
王培宇; 崔秉鉞; Wang, Pei-Yu; Tsui, Bing-Yue |
| 國立交通大學 |
2017-04-21T06:56:49Z |
Investigation Into Gate-to-Source Capacitance Induced by Highly Efficient Band-to-Band Tunneling in p-Channel Ge Epitaxial Tunnel Layer Tunnel FET
|
Wang, Pei-Yu; Tsui, Bing-Yue |
| 國立交通大學 |
2017-04-21T06:56:33Z |
A comprehensive study on the oxidation of 4H-SiC in diluted N2O ambient
|
Tseng, Yuan-Hung; Wu, Tsung-Han; Tsui, Bing-Yue; Yen, Cheng-Tyng; Hung, Chien-Chung; Lee, Chwan-Ying |
| 國立交通大學 |
2017-04-21T06:55:57Z |
Trenched 4H-SiC with tapered sidewall formed by Cl-2/O-2 reactive ion etching
|
Tseng, Yuan-Hung; Tsui, Bing-Yue |
| 國立交通大學 |
2017-04-21T06:55:47Z |
Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure
|
Wang, Pei-Yu; Tsui, Bing-Yue |
| 國立交通大學 |
2017-04-21T06:50:15Z |
Simulation of Grain-Boundary Traps Effect for 3D Vertical Gate NAND Flash Memory Cell : From Structure Geometry to Trap Description
|
Wang, Pei-Yu; Tsui, Bing-Yue |
