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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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2019臺灣學術機構典藏
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Showing items 61-70 of 114  (12 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2018-09-10T08:19:11Z 1.4μW/channel 16-channel EEG/ECoG Processor for Smart Brain Sensor SoC T.-C. Chen;T.-H. Lee;Y.-H. Chen;T.-C. Ma;T.-D. Chuang;C.-J. Chou;C.-H. Yang;T.-H. Lin;L.-G. Chen; T.-C. Chen; T.-H. Lee; Y.-H. Chen; T.-C. Ma; T.-D. Chuang; C.-J. Chou; C.-H. Yang; T.-H. Lin; L.-G. Chen; LIANG-GEE CHEN; TSUNG-HSIEN LIN
臺大學術典藏 2018-09-10T07:43:10Z A Super-Regenerative ASK Receiver with Delta-Sigma Pulse-width Digitizer and SAR-based Fast Frequency Calibration for MICS Applications Y.-H. Liu;H.-H. Liu;T.-H. Lin; Y.-H. Liu; H.-H. Liu; T.-H. Lin; TSUNG-HSIEN LIN
臺大學術典藏 2018-09-10T07:43:10Z A 5GHz Phase-Locked Loop Using Dynamic Phase-Error Compensation Technique for Fast Settling in 0.18-μm CMOS W.-H. Chiu;Y.-H. Huang;T.-H. Lin; W.-H. Chiu; Y.-H. Huang; T.-H. Lin; TSUNG-HSIEN LIN
臺大學術典藏 2018-09-10T07:43:10Z A Time-Domain-Based Self-Calibrated Analog-to-Digital Converter With A Linear Voltage-to-Delay Circuit in 0.18-μm CMOS C.-H. Yang;W.-H. Chiu;T.-H. Lin; C.-H. Yang; W.-H. Chiu; T.-H. Lin; TSUNG-HSIEN LIN
臺大學術典藏 2018-09-10T07:43:10Z A charge pump current missmatch calibration technique for ΔΣ fractional-N PLLs in 0.18-μm CMOS W.-H. Chiu;T.-S. Chang;T.-H. Lin; W.-H. Chiu; T.-S. Chang; T.-H. Lin; TSUNG-HSIEN LIN
臺大學術典藏 2018-09-10T07:43:10Z Delta sigma modulator and method for compensating delta sigma modulators for loop delay Chan-Hsiang Weng;Tsung-Hsien Lin; Chan-Hsiang Weng; Tsung-Hsien Lin; TSUNG-HSIEN LIN
臺大學術典藏 2018-09-10T07:43:10Z A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-μm CMOS K.-C. Liao;P.-S. Huang;W.-H. Chiu;T.-H. Lin; K.-C. Liao; P.-S. Huang; W.-H. Chiu; T.-H. Lin; TSUNG-HSIEN LIN
臺大學術典藏 2018-09-10T07:43:09Z A 200-pJ/b MUX-based RF Transmitter for Implantable Multi-Channel Neural Recording Y.-H. Liu;C.-L. Li;T.-H. Lin; Y.-H. Liu; C.-L. Li; T.-H. Lin; TSUNG-HSIEN LIN
臺大學術典藏 2018-09-10T07:43:09Z Wireless Integrated Network Sensors (WINS) TSUNG-HSIEN LIN; G. Asada; I. Bhatti; T.-H. Lin; S. Natkunanthanan; F. Newberg; R. Rofougaran; A. Sipos; S. Valoff; G. J. Pottie; W. J. Kaiser
臺大學術典藏 2018-09-10T07:43:09Z A Low-Power VLSI Neural Processor Design for Image Data Compression in a SOI CMOS Technology W. Fang; E. Lin; TSUNG-HSIEN LIN

Showing items 61-70 of 114  (12 Page(s) Totally)
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