| 臺大學術典藏 |
2022-09-21T23:31:03Z |
A Lightweight Power Side-Channel Attack Protection Technique with Minimized Overheads Using On-Demand Current Equalizer
|
Cheng, Shih Hao; Lee, Meng Hsueh; Wu, Bing Chen; TSUNG-TE LIU |
| 臺大學術典藏 |
2022-09-21T23:31:02Z |
A Speculative Computation Approach for Energy-Efficient Deep-Neural-Network
|
Zheng, Rui Xuan; Ko, Ya Cheng; TSUNG-TE LIU |
| 臺大學術典藏 |
2022-09-21T23:31:02Z |
A Fully Integrated 1.7mW Attention-Based Automatic Speech Recognition Processor
|
Liou, Yi Long; Hsu, Jui Yang; Chen, Chen Sheng; Liu, Alexander H.; HUNG-YI LEE; TSUNG-TE LIU |
| 臺大學術典藏 |
2022-05-21T23:36:11Z |
CIM-Based Smart Pose Detection Sensors
|
Chou, Jyun Jhe; Chang, Ting Wei; Liu, Xin You; Wu, Tsung Yen; Chen, Yu Kai; Hsu, Ying Tuan; CHIH-WEI CHEN; TSUNG-TE LIU; CHI-SHENG SHIH |
| 臺大學術典藏 |
2021-10-21T23:27:42Z |
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits
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Chen, Tsai Chieh; Pai, Chia Cheng; Hsieh, Yi Zhan; Tseng, Hsiao Yin; Chien-Mo, James; TSUNG-TE LIU; Chiu, I. Wei |
| 臺大學術典藏 |
2021-09-21T23:19:44Z |
A Robust Area-Efficient Physically Unclonable Function With High Machine Learning Attack Resilience in 28-nm CMOS
|
Lai, You Cheng; Yao, Chun Yen; Yang, Shao Hong; Wu, Ying Wei; TSUNG-TE LIU |
| 臺大學術典藏 |
2021-08-21T23:59:07Z |
A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency
|
Wu, Bing Chen; TSUNG-TE LIU |
| 臺大學術典藏 |
2021-05-05T03:27:51Z |
A Variation-Resilient Microprocessor with a Two-Level Timing Error Detection and Correction System in 28-nm CMOS
|
Hong, C.-Y.; Liu, T.-T.; TSUNG-TE LIU |
| 臺大學術典藏 |
2021-05-05T03:27:50Z |
An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications
|
Yeh, L.-Y.; Chen, P.-J.; Pai, C.-C.; Liu, T.-T.; TSUNG-TE LIU |
| 臺大學術典藏 |
2021-02-02T09:21:33Z |
ECC processor over the Koblitz curves with τ-NAF Converter and Square-Square-Add Algorithm
|
Wang, Ting; TSUNG-TE LIU |
| 臺大學術典藏 |
2021-02-02T09:21:30Z |
Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications
|
Lee, Chia Heng; Hsu, Ying Tuan; TSUNG-TE LIU; TZI-DAR CHIUEH |
| 臺大學術典藏 |
2020-06-11T06:34:18Z |
A Voltage-Scalable Low-Power All-Digital Temperature Sensor for On-Chip Thermal Monitoring
|
Ku, C.-Y.;Liu, T.-T.; Ku, C.-Y.; Liu, T.-T.; TSUNG-TE LIU |
| 臺大學術典藏 |
2020-06-11T06:34:18Z |
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine
|
Wu, C.-H.;Chen, T.-S.;Lee, D.-Y.;Liu, T.-T.;Wu, A.-Y.; Wu, C.-H.; Chen, T.-S.; Lee, D.-Y.; Liu, T.-T.; Wu, A.-Y.; TSUNG-TE LIU |
| 臺大學術典藏 |
2020-06-11T06:34:18Z |
A ripple reduction method for switched-capacitor DC-DC voltage converter using fully digital resistance modulation
|
Xie, F.-Y.;Wu, B.-C.;Liu, T.-T.; Xie, F.-Y.; Wu, B.-C.; Liu, T.-T.; TSUNG-TE LIU |
| 臺大學術典藏 |
2020-06-11T06:34:17Z |
Linearity analysis of CMOS passive mixer
|
Liu, T.-T.;Rabaey, J.M.; Liu, T.-T.; Rabaey, J.M.; TSUNG-TE LIU |
| 臺大學術典藏 |
2020-06-11T06:34:17Z |
Ultralow-power design in near-threshold region
|
Markovic, D.;Wang, C.C.;Alarcon, L.P.;Liu, T.-T.;Rabaey, J.M.; Markovic, D.; Wang, C.C.; Alarcon, L.P.; Liu, T.-T.; Rabaey, J.M.; TSUNG-TE LIU |
| 臺大學術典藏 |
2020-06-11T06:34:17Z |
An ultra-low-power dual-mode automatic sleep staging processor using neural-network-based decision tree
|
Chang, S.-Y.;Wu, B.-C.;Liou, Y.-L.;Zheng, R.-X.;Lee, P.-L.;Chiueh, T.-D.;Liu, T.-T.; Chang, S.-Y.; Wu, B.-C.; Liou, Y.-L.; Zheng, R.-X.; Lee, P.-L.; Chiueh, T.-D.; Liu, T.-T.; TSUNG-TE LIU |
| 臺大學術典藏 |
2020-06-11T06:34:16Z |
Filter-based dual-voltage architecture for low-power long-word TCAM design
|
Chen, T.-S.;Lee, D.-Y.;Liu, T.-T.;Wu, A.-Y.; Chen, T.-S.; Lee, D.-Y.; Liu, T.-T.; Wu, A.-Y.; TSUNG-TE LIU |
| 臺大學術典藏 |
2020-06-11T06:34:16Z |
Variation-Resilient Design Techniques for Energy-Constrained Systems.
|
Wu, Bing-Chen;Liu, Tsung-Te; Wu, Bing-Chen; Liu, Tsung-Te; TSUNG-TE LIU |
| 臺大學術典藏 |
2019-10-24T07:57:22Z |
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing
|
吳安宇;AN-YEU(ANDY) WU;An-Yeu (Andy) Wu;Tsung-Te Liu;Ding-Yuan Lee;Ting-Sheng Chen; Ting-Sheng Chen; Ding-Yuan Lee; Tsung-Te Liu; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU; 吳安宇 |
| 臺大學術典藏 |
2019-09-16T05:35:55Z |
An ultra-low-power dual-mode automatic sleep staging processor using neural-network-based decision tree
|
TZI-DAR CHIUEH; TSUNG-TE LIU; PEI-LIN LEE; Zheng, Rui Xuan; Liou, Yi Long; Wu, Bing Chen; Chang, Shang Yuan; TSUNG-TE LIU;TZI-DAR CHIUEH;PEI-LIN LEE;Zheng, Rui Xuan;Liou, Yi Long;Wu, Bing Chen;Chang, Shang Yuan |
| 臺大學術典藏 |
2018-09-10T15:26:25Z |
An Energy-Efficient Resilient Flip-Flop Circuit with Built-In Timing-Error Detection and Correction
|
J. M. Huang;T. T. Liu;T. D. Chiueh; J. M. Huang; T. T. Liu; T. D. Chiueh; TZI-DAR CHIUEH; TSUNG-TE LIU |
| 臺大學術典藏 |
2018-09-10T09:50:56Z |
A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression
|
Liu, T.-T.;Rabaey, J.M.; Liu, T.-T.; Rabaey, J.M.; TSUNG-TE LIU |
| 臺大學術典藏 |
2018-09-10T09:50:56Z |
TEASE: A Systematic Analysis Framework for Early Evaluation of FinFET-based Advanced Technology Nodes
|
P. Zuber; T.-T. Liu; B. Chava; B. Ballal; P. Royer; K. Croes; B. Rogier; R. Julien; A. Mercha; M. Badaroglu,; D. Verkest; A. Mallik; P. Zuber; T.-T. Liu; B. Chava; B. Ballal; P. Royer; K. Croes; B. Rogier; R. Julien; A. Mercha; M. Badaroglu; D. Verkest; TSUNG-TE LIU |
| 臺大學術典藏 |
2018-09-10T09:25:34Z |
Statistical Analysis and Optimization of Asynchronous Circuits
|
T.-T. Liu;J. Rabaey; T.-T. Liu; J. Rabaey; TSUNG-TE LIU |
