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Showing items 1-6 of 6 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:16:40Z |
On-chip bus encoding for power minimization under delay constraint
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Lin, Tzu-Wei; Tu, Shang-Wei; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:15:41Z |
RLC coupling-aware simulation and on-chip bus encoding for delay reduction
|
Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
2006-10 |
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
|
Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 臺大學術典藏 |
2006-10 |
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
|
Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang; Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
2003 |
Inductance Modeling for On-Chip Interconnects
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Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen; Chen, Tai-Chen; Jou, Jing-Yang |
| 臺大學術典藏 |
2003 |
Inductance Modeling for On-Chip Interconnects
|
Chen, Tai-Chen; Jou, Jing-Yang; Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen; Chen, Tai-Chen; Jou, Jing-Yang; Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen |
Showing items 1-6 of 6 (1 Page(s) Totally)
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