臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

	English \| 正體中文 \| 简体中文 \| 2823024
	???header.visitor??? : 30257738 ???header.onlineuser??? : 1116 ???header.sponsordeclaration???

???search.scope???

???search.advance???

???search.login???

???search.administrator???

臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

???ui.leftmenu.abouttair???
	???ui.leftmenu.explanation???

???ui.leftmenu.bartitle???
	Repositories
	Author
	Title
	Date
	???ui.leftmenu.statisticschart???
	???ui.leftmenu.realtimefacts???
	???ui.leftmenu.trend???

???index.news???
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

???ui.leftmenu.copyrighttitle???
	???ui.leftmenu.copyrightpublisher???
	???ui.leftmenu.copyrightconference???

???ui.leftmenu.link???
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"w j h lin"???jsp.browse.items-by-author.description???

???jsp.browse.items-by-author.back???
???jsp.browse.items-by-author.order1???	???jsp.browse.items-by-author.order2???

Showing items 1-2 of 2 (1 Page(s) Totally)
1
View [10|25|50] records per page

Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:41:37Z	0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications	W. J. H. Lin;C. Y. Chien;J. B. Kuo; W. J. H. Lin; C. Y. Chien; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:37Z	0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications	W. J. H. Lin;C. Y. Chien;J. B. Kuo; W. J. H. Lin; C. Y. Chien; J. B. Kuo; JAMES-B KUO

Showing items 1-2 of 2 (1 Page(s) Totally)
1
View [10|25|50] records per page