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Institution Date Title Author
國立交通大學 2015-12-04T07:03:10Z MULTI-PORT SRAM WITH SHARED WRITE BIT-LINE ARCHITECTURE AND SELECTIVE READ PATH FOR LOW POWER OPERATION HWANG Wei; WANG Dao-Ping
國立交通大學 2014-12-16T06:14:46Z TEN-TRANSISTOR DUAL-PORT SRAM WITH SHARED BIT-LINE ARCHITECTURE HWANG Wei; WANG Dao-Ping
國立交通大學 2014-12-16T06:13:47Z Ten-transistor dual-port SRAM with shared bit-line architecture Hwang Wei; Wang Dao-Ping
國立交通大學 2014-12-12T02:33:37Z 低功率多埠靜態隨機存取記憶體設計:寫入與讀取改善技術 王道平; Wang, Dao-Ping; 黃威; Hwang, Wei
國立交通大學 2014-12-08T15:35:28Z Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors Wang, Dao-Ping; Lin, Hon-Jarn; Chuang, Ching-Te; Hwang, Wei

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