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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Institution Date Title Author
國立交通大學 2017-04-21T06:49:16Z Custom 6-R, 2-or 4-W Multi-Port Register Files in an ASIC SOC with a DVFS Window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS Technology Hsieh, Henry; Dhong, Sang H.; Lin, Cheng-Chung; Kuo, Ming-Zhang; Tseng, Kuo-Feng; Yang, Ping-Lin; Huang, Kevin; Wang, Min-Jer; Hwang, Wei
國立交通大學 2017-04-21T06:48:47Z A 16kB Tile-able SRAM Macro Prototype for an Operating Window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS Kuo, Ming-Zhang; Hsieh, Henry; Dhong, Sang; Yang, Ping-Lin; Lin, Cheng-Chung; Tseng, Ryan; Huang, Kevin; Wang, Min-Jer; Hwang, Wei
國立交通大學 2017-04-21T06:48:47Z A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SOC Dhong, Sang; Guo, Richard; Kuo, Ming-Zhang; Yang, Ping-Lin; Lin, Cheng-Chung; Huang, Kevin; Wang, Min-Jer; Hwang, Wei
國立交通大學 2014-12-08T15:35:53Z A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application Lin, Mu-Shan; Tsai, Chien-Chun; Chang, Chih-Hsien; Huang, Wen-Hung; Hsu, Ying-Yu; Yang, Shu-Chun; Fu, Chin-Ming; Chou, Mao-Hsuan; Huang, Tien-Chien; Chen, Ching-Fang; Huang, Tze-Chiang; Adham, Saman; Wang, Min-Jer; Shen, William Wu; Mehta, Ashok

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