| 國立交通大學 |
2014-12-12T01:38:14Z |
數位校正式比較器及其在快閃型類比數位轉換器上的應用
|
黃鈞正; Huang, Chun-Cheng; 吳介琮; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-12T01:22:02Z |
低功率類比數位轉換器之設計技術
|
鍾勇輝; Chung, Yung-Hui; 吳介琮; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-12T01:21:39Z |
高速電流引導式數位類比轉換器
|
曾偉信; Tseng, Wei-Hsin; 吳介琮; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-12T01:21:26Z |
低功率低電壓雙路管線式類比數位轉換器
|
翟芸; Chai, Angelia Yolanda; 吳介琮; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:39:30Z |
A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration
|
Huang, Chun-Cheng; Wang, Chung-Yi; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:35:45Z |
A 1-V 100-dB Dynamic Range 24.4-kHz Bandwidth Delta-Sigma Modulator
|
Chang, Chia-Ling; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:33:11Z |
Background Calibration of Integrator Leakage in Discrete-Time Delta-Sigma Modulators
|
Wu, Su-Hao; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:31:53Z |
A 81-dB Dynamic Range 16-MHz Bandwidth Delta Sigma Modulator Using Background Calibration
|
Wu, Su-Hao; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:30:05Z |
A 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opamps
|
Fang, Bing-Nan; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:29:24Z |
A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation
|
Fang, Bing-Nan; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:28:51Z |
A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC
|
Chai, Yun; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:24:43Z |
A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration
|
Lee, Zwei-Mei; Wang, Cheng-Yeh; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:21:05Z |
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
|
Chung, Yung-Hui; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:21:00Z |
A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With > 70 dB SFDR up to 500 MHz
|
Tseng, Wei-Hsin; Fan, Chi-Wei; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:20:30Z |
ADC Clock Jitter Measurement and Correction Using a Stochastic TDC
|
Fan, Chi-Wei; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:13:52Z |
A robust and fast digital background calibration technique for pipelined ADCs
|
Fan, Jen-Lin; Wang, Chung-Yi; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:11:50Z |
A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques
|
Huang, Chun-Cheng; Wang, Chung-Yi; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:09:21Z |
A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection
|
Wang, Chung-Yi; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:08:20Z |
Jitter Measurement and Compensation for Analog-to-Digital Converters
|
Fan, Chi-Wei; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:07:13Z |
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
|
Chung, Yung-Hui; Wu, Jieh-Tsorng |
| 國立交通大學 |
2014-12-08T15:05:23Z |
A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration
|
Lee, Zwei-Mei; Wang, Cheng-Yeh; Wu, Jieh-Tsorng |
