臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T05:26:57Z	Automatic Partitioner for Behavior Level Distributed Logic Simulation	K. H. Chang; J. Y. Kang; H. W. Wang; W. T. Tu; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:59:13Z	Techniques to Reduce Synchronization in Distributed Parallel Logic Simulation	K. H. Chang; W. T. Tu; H. W. Wang; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:59:12Z	A Temporal Assertion Extension to Verilog	K. H. Chang; W. T. Tu; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:59:10Z	Automatic Partitioner for Distributed Parallel Logic Simulation	K. H. Chang; H. W. Wang; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:59:10Z	System Level Assertion-Based Verification Environment for PCI/PCI-X and PCI-Express	C. C; Yu; K. H. Chang; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:35:24Z	A PCI-X Verification Environment Using C and Verilog	K. H. Chang; Y. C. Su; W. T. Tu; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:35:24Z	A Tag-Augmented Temporal Logic Checker	K. H. Chang; W. T. Tu; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:35:23Z	Automatic Partitioner for Distributed Simulation	K. H. Chang; W. T. Tu; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:15:11Z	An Optimization-based Multiple-Voltage Scaling Technique for Low Power CMOS Digital Design	Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T03:50:21Z	An Optimization-Based Low-Power Voltage Scaling Techniques Using Multiple Supply Voltages	Y. J. Yeh; S. Y. Kuo; SY-YEN KUO

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