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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"yan jin tai"的相關文件
顯示項目 1-25 / 96 (共4頁)
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| 國立交通大學 |
2020-07-01T05:21:48Z |
Construction of Delay-Driven GNR Routing Tree
|
Yan, Jin-Tai; Yen, Chia-Heng |
| 國立交通大學 |
2019-04-02T06:04:49Z |
Feasible Assignment of Micro-Bumps in 3D ICs
|
Yan, Jin-Tai; Yen, Chia-Heng |
| 國立交通大學 |
2017-04-21T06:49:38Z |
Timing-Constrained Yield-Driven Redundant Via Insertion
|
Yan, Jin-Tai; Chen, Zhi-Wei; Chiang, Bo-Yi; Lee, Yu-Min |
| 國立交通大學 |
2014-12-12T02:14:17Z |
在聚集晶元佈局上K-方電路分割,擺置改良,區域定義和繞線順序設計之設計
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顏金泰; Yan, Jin Tai; 蕭培墉; Xiao, Pei Yong |
| 國立交通大學 |
2014-12-12T02:06:45Z |
一個(M+1)位元迴饋分割式通訊協定
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顏金泰; YAN,JIN-TAI; 簡榮宏; JIAN,RONG-HONG |
| 國立交通大學 |
2014-12-08T15:24:49Z |
Floorplan-aware decoupling capacitance budgeting on equivalent circuit model
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Yan, Jin-Tai; Lin, Kai-Ping; Luo, Yue-Fong |
| 國立交通大學 |
2014-12-08T15:24:49Z |
Optimal shielding insertion for inductive noise avoidance
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Yan, Jin-Tai; Lin, Kuen-Ming; Chen, Yen-Hsiang |
| 國立交通大學 |
2014-12-08T15:02:59Z |
Block-Level Thermal Model for Floorplan Stage in VLSI Design Flow
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Lin, Shun-Hua; Yan, Jin-Tai; Chiueh, Herming |
| 中華大學 |
2013 |
Routability-Constrained Multi-Bit Flip-Flop Construction for Clock Power Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2013 |
Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2013 |
Timing-Constrained Replacement Using Spare Cells for Design Changes
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2013 |
Post-Layout Redundant Wire Insertion for Fixing Min-Delay Violations
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Resource-Constrained Link Insertion for Delay Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Efficient Assignment of Inter-Die Signals for Die-Stacking SiP Design
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Utilization of Multi-Bit Flip-Flops for Clock Power Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Density-Reduction-Oriented Layer Assignment for Rectangle Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Top-Down-Based Symmetrical Buffered Clock Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Post-Layout OPE-Predicted Redundant Wire Insertion for Clock Skew Minimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Direction-Constrained Layer Assignment for Rectangle Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
IO Connection Assignment and RDL Routing for Flip-Chip Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Timing-Constrained I/O Buffer Placement for Flip-Chip Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-Aware Length-Matching Bus Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Pre-Assignment RDL Routing via Extraction of Maximal Net Sequence
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顏金泰; YAN, JIN-TAI |
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