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"yan jin tai"
Showing items 81-90 of 96 (10 Page(s) Totally)
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| 中華大學 |
2005 |
Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Sliceable Transformation of Non-Slicing Floorplans Based on Vacant Block Insertion in LB-packing Process
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction with Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
LB-Packing-Based Floorplan Design on DBL Representation
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Floorplan-Aware Steiner Tree Reconstruction for Optimal Buffer Insertion
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Optimal Shielding Insertion for Inductive Noise Avoidance
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2004 |
Timing-Constrained Congestion-Driven Global Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2004 |
Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization
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顏金泰; YAN, JIN-TAI |
Showing items 81-90 of 96 (10 Page(s) Totally)
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