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Showing items 76-85 of 190 (19 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T06:31:00Z |
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
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Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T06:30:59Z |
Temporal floorplanning using the three-dimensional transitive closure subGraph
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Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T06:27:37Z |
An architectural co-synthesis algorithm for energy-aware network-on-chip design
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Hung, Wei-Hsuan;Chen, Yi-Jung;Yang, Chia-Lin;Chang, Yen-Sheng;Su, Alan P.; Hung, Wei-Hsuan; Chen, Yi-Jung; Yang, Chia-Lin; Chang, Yen-Sheng; Su, Alan P.; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T05:20:41Z |
Reconfigurable platform for content science research
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Shih, C.-S.; Yang, C.-L.; Ku, M.-K.; Kuo, T.-W.; Chien, S.-Y.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN; Shih, Chi-Sheng; Yang, Chia-Lin; TEI-WEI KUO; YAO-WEN CHANG; SHAO-YI CHIEN |
| 臺大學術典藏 |
2018-09-10T05:18:22Z |
Software-controlled cache architecture for energy efficiency
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Yang, Chia-Lin;Tseng, Hung-Wei;Ho, Chia-Chiang;Wu, Ja-Ling; Yang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; Wu, Ja-Ling; JA-LING WU; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T04:31:08Z |
Smart cache: An energy-efficient D-cache for a software MPEG-2 video decoder
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Yang, Chia-Lin;Tseng, Hung-Wei;Ho, Chia-Chiang; Yang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T03:28:17Z |
Push vs. pull: Data movement for linked data structures
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Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG |
| 國立交通大學 |
2018-08-21T05:57:06Z |
Analyzing OpenCL 2.0 Workloads Using a Heterogeneous CPU-GPU Simulator
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Wang, Li; Tsai, Ren-Wei; Wang, Shao-Chung; Chen, Kun-Chih; Wang, Po-Han; Cheng, Hsiang-Yun; Lee, Yi-Chung; Shu, Sheng-Jie; Yang, Chun-Chieh; Hsu, Min-Yih; Kan, Li-Chen; Lee, Chao-Lin; Yu, Tzu-Chieh; Peng, Rih-Ding; Yang, Chia-Lin; Hwang, Yuan-Shin; Lee, Jenq-Kuen; Tsao, Shiao-Li; Ouhyoung, Ming |
| 臺大學術典藏 |
2018-07-05T01:59:29Z |
A Space-Efficient Caching Mechanism for Flash-Memory Address Translation
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Yang, Chia-Lin; Kuo, Tei-Wei; Wu, Chin-Hsien; Wu, Chin-Hsien; Kuo, Tei-Wei; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-07-05T01:55:22Z |
Tolerating Memory Latency Through Push Prefetching for Pointer-Intensive Applications
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Lee, Chien-Hao; Tseng, Hung-Wei; Lebeck, Alvin R.; Yang, Chia-Lin; Lebeck, Alvin R.; Tseng, Hung-Wei; Lee, Chien-Hao; Yang, Chia-Lin |
Showing items 76-85 of 190 (19 Page(s) Totally)
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